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Merged
merged 4 commits into from
May 22, 2025
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[InferAddressSpaces] Handle llvm.lifetime #141045

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4175c7d
[InferAddressSpaces] Handle llvm.lifetime
May 22, 2025
3c4e628
fixup! [InferAddressSpaces] Handle llvm.lifetime
May 22, 2025
0e37754
Remove empty line
arsenm May 22, 2025
1db5ba4
fixup! fixup! [InferAddressSpaces] Handle llvm.lifetime
May 22, 2025
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14 changes: 14 additions & 0 deletions llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -428,6 +428,14 @@ bool InferAddressSpacesImpl::rewriteIntrinsicOperands(IntrinsicInst *II,
II->replaceUsesOfWith(OldV, NewV);
return true;
}
case Intrinsic::lifetime_start:
case Intrinsic::lifetime_end: {
Function *NewDecl = Intrinsic::getOrInsertDeclaration(
M, II->getIntrinsicID(), {NewV->getType()});
II->setArgOperand(1, NewV);
II->setCalledFunction(NewDecl);
return true;
}
default: {
Value *Rewrite = TTI->rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
if (!Rewrite)
Expand Down Expand Up @@ -479,6 +487,12 @@ void InferAddressSpacesImpl::collectRewritableIntrinsicOperands(

break;
}
case Intrinsic::lifetime_start:
case Intrinsic::lifetime_end: {
appendsFlatAddressExpressionToPostorderStack(II->getArgOperand(1),
PostorderStack, Visited);
break;
}
default:
SmallVector<int, 2> OpIndexes;
if (TTI->collectFlatAddressOperands(OpIndexes, IID)) {
Expand Down
23 changes: 23 additions & 0 deletions llvm/test/Transforms/InferAddressSpaces/AMDGPU/lifetime.ll
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@@ -0,0 +1,23 @@
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=infer-address-spaces %s | FileCheck %s


define i32 @lifetime_flat_pointer() {
; CHECK-LABEL: define i32 @lifetime_flat_pointer() {
; CHECK-NEXT: [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5)
; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[ALLOCA]])
; CHECK-NEXT: store i32 1, ptr addrspace(5) [[ALLOCA]], align 4
; CHECK-NEXT: %ret = load i32, ptr addrspace(5) [[ALLOCA]], align 4
; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[ALLOCA]])
; CHECK-NEXT: ret i32 %ret
;
%alloca = alloca i32, align 4, addrspace(5)
%flat = addrspacecast ptr addrspace(5) %alloca to ptr
call void @llvm.lifetime.start.p0(i64 4 , ptr %flat)
store i32 1, ptr %flat, align 4
%ret = load i32, ptr %flat, align 4
call void @llvm.lifetime.end.p0(i64 4 , ptr %flat)
ret i32 %ret
}

declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture)
42 changes: 42 additions & 0 deletions llvm/test/Transforms/InferAddressSpaces/NVPTX/lifetime.ll
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@@ -0,0 +1,42 @@
; RUN: opt -S -passes=infer-address-spaces %s | FileCheck %s

target triple = "nvptx64-nvidia-cuda"

define i32 @lifetime_flat_pointer() {
; CHECK-LABEL: define i32 @lifetime_flat_pointer() {
; CHECK-NEXT: [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5)
; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[ALLOCA]])
; CHECK-NEXT: store i32 1, ptr addrspace(5) [[ALLOCA]], align 4
; CHECK-NEXT: %ret = load i32, ptr addrspace(5) [[ALLOCA]], align 4
; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[ALLOCA]])
; CHECK-NEXT: ret i32 %ret
;
%alloca = alloca i32, align 4, addrspace(5)
%flat = addrspacecast ptr addrspace(5) %alloca to ptr
call void @llvm.lifetime.start.p0(i64 4 , ptr %flat)
store i32 1, ptr %flat, align 4
%ret = load i32, ptr %flat, align 4
call void @llvm.lifetime.end.p0(i64 4 , ptr %flat)
ret i32 %ret
}

define i32 @lifetime_flat_pointer2() {
; CHECK-LABEL: define i32 @lifetime_flat_pointer2() {
; CHECK-NEXT: [[ALLOCA:%.*]] = alloca i32, align 4
; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[ALLOCA]] to ptr addrspace(5)
; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[TMP1]])
; CHECK-NEXT: store i32 1, ptr addrspace(5) [[TMP1]], align 4
; CHECK-NEXT: %ret = load i32, ptr addrspace(5) [[TMP1]], align 4
; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[TMP1]])
; CHECK-NEXT: ret i32 %ret
;
%alloca = alloca i32, align 4
call void @llvm.lifetime.start.p5(i64 4 , ptr %alloca)
store i32 1, ptr %alloca, align 4
%ret = load i32, ptr %alloca, align 4
call void @llvm.lifetime.end.p5(i64 4 , ptr %alloca)
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Suggested change
call void @llvm.lifetime.start.p5(i64 4 , ptr %alloca)
store i32 1, ptr %alloca, align 4
%ret = load i32, ptr %alloca, align 4
call void @llvm.lifetime.end.p5(i64 4 , ptr %alloca)
call void @llvm.lifetime.start.p5(i64 4, ptr %alloca)
store i32 1, ptr %alloca, align 4
%ret = load i32, ptr %alloca, align 4
call void @llvm.lifetime.end.p5(i64 4, ptr %alloca)

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@QiYueFeiXue QiYueFeiXue May 22, 2025 •
edited
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The second one is a typo. Please check if it is needed in this scene. The following is the difference between IR before and after this PR:

%alloca = alloca i32, align 4
call void @llvm.lifetime.start.p0(i64 4 , ptr %alloca)
store i32 1, ptr %alloca, align 4
%ret = load i32, ptr %alloca, align 4
call void @llvm.lifetime.end.p0(i64 4 , ptr %alloca)
ret i32 %ret

before PR:

%alloca = alloca i32, align 4
%1 = addrspacecast ptr %alloca to ptr addrspace(5)
%2 = addrspacecast ptr addrspace(5) %1 to ptr
%3 = addrspacecast ptr addrspace(5) %1 to ptr
call void @llvm.lifetime.start.p0(i64 4, ptr %2)
store i32 1, ptr addrspace(5) %1, align 4
%ret = load i32, ptr addrspace(5) %1, align 4
call void @llvm.lifetime.end.p0(i64 4, ptr %3)
ret i32 %ret

after PR:

%alloca = alloca i32, align 4
%1 = addrspacecast ptr %alloca to ptr addrspace(5)
call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) %1)
store i32 1, ptr addrspace(5) %1, align 4
%ret = load i32, ptr addrspace(5) %1, align 4
call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) %1)
ret i32 %ret

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OK, so it demonstrates a possible phase ordering with the alloca lowering PTX does, I suppose that's useful, if you adjust the test to look like this "before PR" version

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Got it, done, thanks

ret i32 %ret
}

declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture)