[InferAddressSpaces] Handle llvm.lifetime #141045

QiYueFeiXue · 2025-05-22T11:49:13Z

No description provided.

github-actions · 2025-05-22T11:49:34Z

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llvmbot · 2025-05-22T11:50:04Z

@llvm/pr-subscribers-backend-amdgpu

Author: QiYue (QiYueFeiXue)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/141045.diff

3 Files Affected:

(modified) llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp (+14)
(added) llvm/test/Transforms/InferAddressSpaces/AMDGPU/lifetime.ll (+23)
(added) llvm/test/Transforms/InferAddressSpaces/NVPTX/lifetime.ll (+24)

diff --git a/llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp b/llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp
index 1b7cecc7ceb6a..66836ef05d5db 100644
--- a/llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp
+++ b/llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp
@@ -428,6 +428,14 @@ bool InferAddressSpacesImpl::rewriteIntrinsicOperands(IntrinsicInst *II,
     II->replaceUsesOfWith(OldV, NewV);
     return true;
   }
+  case Intrinsic::lifetime_start:
+  case Intrinsic::lifetime_end: {
+    Function *NewDecl = Intrinsic::getOrInsertDeclaration(
+        M, II->getIntrinsicID(), {NewV->getType()});
+    II->setArgOperand(1, NewV);
+    II->setCalledFunction(NewDecl);
+    return true;
+  }
   default: {
     Value *Rewrite = TTI->rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
     if (!Rewrite)
@@ -479,6 +487,12 @@ void InferAddressSpacesImpl::collectRewritableIntrinsicOperands(
 
     break;
   }
+  case Intrinsic::lifetime_start:
+  case Intrinsic::lifetime_end: {
+    appendsFlatAddressExpressionToPostorderStack(II->getArgOperand(1),
+                                                 PostorderStack, Visited);
+    break;
+  }
   default:
     SmallVector<int, 2> OpIndexes;
     if (TTI->collectFlatAddressOperands(OpIndexes, IID)) {
diff --git a/llvm/test/Transforms/InferAddressSpaces/AMDGPU/lifetime.ll b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/lifetime.ll
new file mode 100644
index 0000000000000..291faa7ea9ef4
--- /dev/null
+++ b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/lifetime.ll
@@ -0,0 +1,23 @@
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=infer-address-spaces %s | FileCheck %s
+
+
+define i32 @lifetime_flat_pointer() {
+; CHECK-LABEL: define i32 @lifetime_flat_pointer() {
+; CHECK-NEXT:    [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5)
+; CHECK-NEXT:    call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[ALLOCA]])
+; CHECK-NEXT:    store i32 1, ptr addrspace(5) [[ALLOCA]], align 4
+; CHECK-NEXT:    %ret = load i32, ptr addrspace(5) [[ALLOCA]], align 4
+; CHECK-NEXT:    call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[ALLOCA]])
+; CHECK-NEXT:    ret i32 %ret
+;
+  %alloca = alloca i32, align 4, addrspace(5)
+  %flat = addrspacecast ptr addrspace(5) %alloca to ptr
+  call void @llvm.lifetime.start.p0(i64 4 , ptr %flat)
+  store i32 1, ptr %flat, align 4
+  %ret = load i32, ptr %flat, align 4
+  call void @llvm.lifetime.end.p0(i64 4 , ptr %flat)
+  ret i32 %ret
+}
+
+declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture)
+declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture)
\ No newline at end of file
diff --git a/llvm/test/Transforms/InferAddressSpaces/NVPTX/lifetime.ll b/llvm/test/Transforms/InferAddressSpaces/NVPTX/lifetime.ll
new file mode 100644
index 0000000000000..05e46456c8bf9
--- /dev/null
+++ b/llvm/test/Transforms/InferAddressSpaces/NVPTX/lifetime.ll
@@ -0,0 +1,24 @@
+; RUN: opt -S -passes=infer-address-spaces %s | FileCheck %s
+
+target triple = "nvptx64-nvidia-cuda"
+
+define i32 @lifetime_flat_pointer() {
+; CHECK-LABEL: define i32 @lifetime_flat_pointer() {
+; CHECK-NEXT:    [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5)
+; CHECK-NEXT:    call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[ALLOCA]])
+; CHECK-NEXT:    store i32 1, ptr addrspace(5) [[ALLOCA]], align 4
+; CHECK-NEXT:    %ret = load i32, ptr addrspace(5) [[ALLOCA]], align 4
+; CHECK-NEXT:    call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[ALLOCA]])
+; CHECK-NEXT:    ret i32 %ret
+;
+  %alloca = alloca i32, align 4, addrspace(5)
+  %flat = addrspacecast ptr addrspace(5) %alloca to ptr
+  call void @llvm.lifetime.start.p0(i64 4 , ptr %flat)
+  store i32 1, ptr %flat, align 4
+  %ret = load i32, ptr %flat, align 4
+  call void @llvm.lifetime.end.p0(i64 4 , ptr %flat)
+  ret i32 %ret
+}
+
+declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture)
+declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture)

llvmbot · 2025-05-22T11:50:05Z

@llvm/pr-subscribers-backend-nvptx

Author: QiYue (QiYueFeiXue)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/141045.diff

3 Files Affected:

(modified) llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp (+14)
(added) llvm/test/Transforms/InferAddressSpaces/AMDGPU/lifetime.ll (+23)
(added) llvm/test/Transforms/InferAddressSpaces/NVPTX/lifetime.ll (+24)

diff --git a/llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp b/llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp
index 1b7cecc7ceb6a..66836ef05d5db 100644
--- a/llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp
+++ b/llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp
@@ -428,6 +428,14 @@ bool InferAddressSpacesImpl::rewriteIntrinsicOperands(IntrinsicInst *II,
     II->replaceUsesOfWith(OldV, NewV);
     return true;
   }
+  case Intrinsic::lifetime_start:
+  case Intrinsic::lifetime_end: {
+    Function *NewDecl = Intrinsic::getOrInsertDeclaration(
+        M, II->getIntrinsicID(), {NewV->getType()});
+    II->setArgOperand(1, NewV);
+    II->setCalledFunction(NewDecl);
+    return true;
+  }
   default: {
     Value *Rewrite = TTI->rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
     if (!Rewrite)
@@ -479,6 +487,12 @@ void InferAddressSpacesImpl::collectRewritableIntrinsicOperands(
 
     break;
   }
+  case Intrinsic::lifetime_start:
+  case Intrinsic::lifetime_end: {
+    appendsFlatAddressExpressionToPostorderStack(II->getArgOperand(1),
+                                                 PostorderStack, Visited);
+    break;
+  }
   default:
     SmallVector<int, 2> OpIndexes;
     if (TTI->collectFlatAddressOperands(OpIndexes, IID)) {
diff --git a/llvm/test/Transforms/InferAddressSpaces/AMDGPU/lifetime.ll b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/lifetime.ll
new file mode 100644
index 0000000000000..291faa7ea9ef4
--- /dev/null
+++ b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/lifetime.ll
@@ -0,0 +1,23 @@
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=infer-address-spaces %s | FileCheck %s
+
+
+define i32 @lifetime_flat_pointer() {
+; CHECK-LABEL: define i32 @lifetime_flat_pointer() {
+; CHECK-NEXT:    [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5)
+; CHECK-NEXT:    call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[ALLOCA]])
+; CHECK-NEXT:    store i32 1, ptr addrspace(5) [[ALLOCA]], align 4
+; CHECK-NEXT:    %ret = load i32, ptr addrspace(5) [[ALLOCA]], align 4
+; CHECK-NEXT:    call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[ALLOCA]])
+; CHECK-NEXT:    ret i32 %ret
+;
+  %alloca = alloca i32, align 4, addrspace(5)
+  %flat = addrspacecast ptr addrspace(5) %alloca to ptr
+  call void @llvm.lifetime.start.p0(i64 4 , ptr %flat)
+  store i32 1, ptr %flat, align 4
+  %ret = load i32, ptr %flat, align 4
+  call void @llvm.lifetime.end.p0(i64 4 , ptr %flat)
+  ret i32 %ret
+}
+
+declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture)
+declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture)
\ No newline at end of file
diff --git a/llvm/test/Transforms/InferAddressSpaces/NVPTX/lifetime.ll b/llvm/test/Transforms/InferAddressSpaces/NVPTX/lifetime.ll
new file mode 100644
index 0000000000000..05e46456c8bf9
--- /dev/null
+++ b/llvm/test/Transforms/InferAddressSpaces/NVPTX/lifetime.ll
@@ -0,0 +1,24 @@
+; RUN: opt -S -passes=infer-address-spaces %s | FileCheck %s
+
+target triple = "nvptx64-nvidia-cuda"
+
+define i32 @lifetime_flat_pointer() {
+; CHECK-LABEL: define i32 @lifetime_flat_pointer() {
+; CHECK-NEXT:    [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5)
+; CHECK-NEXT:    call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[ALLOCA]])
+; CHECK-NEXT:    store i32 1, ptr addrspace(5) [[ALLOCA]], align 4
+; CHECK-NEXT:    %ret = load i32, ptr addrspace(5) [[ALLOCA]], align 4
+; CHECK-NEXT:    call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[ALLOCA]])
+; CHECK-NEXT:    ret i32 %ret
+;
+  %alloca = alloca i32, align 4, addrspace(5)
+  %flat = addrspacecast ptr addrspace(5) %alloca to ptr
+  call void @llvm.lifetime.start.p0(i64 4 , ptr %flat)
+  store i32 1, ptr %flat, align 4
+  %ret = load i32, ptr %flat, align 4
+  call void @llvm.lifetime.end.p0(i64 4 , ptr %flat)
+  ret i32 %ret
+}
+
+declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture)
+declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture)

llvmbot · 2025-05-22T11:50:05Z

@llvm/pr-subscribers-llvm-transforms

Author: QiYue (QiYueFeiXue)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/141045.diff

3 Files Affected:

(modified) llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp (+14)
(added) llvm/test/Transforms/InferAddressSpaces/AMDGPU/lifetime.ll (+23)
(added) llvm/test/Transforms/InferAddressSpaces/NVPTX/lifetime.ll (+24)

diff --git a/llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp b/llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp
index 1b7cecc7ceb6a..66836ef05d5db 100644
--- a/llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp
+++ b/llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp
@@ -428,6 +428,14 @@ bool InferAddressSpacesImpl::rewriteIntrinsicOperands(IntrinsicInst *II,
     II->replaceUsesOfWith(OldV, NewV);
     return true;
   }
+  case Intrinsic::lifetime_start:
+  case Intrinsic::lifetime_end: {
+    Function *NewDecl = Intrinsic::getOrInsertDeclaration(
+        M, II->getIntrinsicID(), {NewV->getType()});
+    II->setArgOperand(1, NewV);
+    II->setCalledFunction(NewDecl);
+    return true;
+  }
   default: {
     Value *Rewrite = TTI->rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
     if (!Rewrite)
@@ -479,6 +487,12 @@ void InferAddressSpacesImpl::collectRewritableIntrinsicOperands(
 
     break;
   }
+  case Intrinsic::lifetime_start:
+  case Intrinsic::lifetime_end: {
+    appendsFlatAddressExpressionToPostorderStack(II->getArgOperand(1),
+                                                 PostorderStack, Visited);
+    break;
+  }
   default:
     SmallVector<int, 2> OpIndexes;
     if (TTI->collectFlatAddressOperands(OpIndexes, IID)) {
diff --git a/llvm/test/Transforms/InferAddressSpaces/AMDGPU/lifetime.ll b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/lifetime.ll
new file mode 100644
index 0000000000000..291faa7ea9ef4
--- /dev/null
+++ b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/lifetime.ll
@@ -0,0 +1,23 @@
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=infer-address-spaces %s | FileCheck %s
+
+
+define i32 @lifetime_flat_pointer() {
+; CHECK-LABEL: define i32 @lifetime_flat_pointer() {
+; CHECK-NEXT:    [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5)
+; CHECK-NEXT:    call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[ALLOCA]])
+; CHECK-NEXT:    store i32 1, ptr addrspace(5) [[ALLOCA]], align 4
+; CHECK-NEXT:    %ret = load i32, ptr addrspace(5) [[ALLOCA]], align 4
+; CHECK-NEXT:    call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[ALLOCA]])
+; CHECK-NEXT:    ret i32 %ret
+;
+  %alloca = alloca i32, align 4, addrspace(5)
+  %flat = addrspacecast ptr addrspace(5) %alloca to ptr
+  call void @llvm.lifetime.start.p0(i64 4 , ptr %flat)
+  store i32 1, ptr %flat, align 4
+  %ret = load i32, ptr %flat, align 4
+  call void @llvm.lifetime.end.p0(i64 4 , ptr %flat)
+  ret i32 %ret
+}
+
+declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture)
+declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture)
\ No newline at end of file
diff --git a/llvm/test/Transforms/InferAddressSpaces/NVPTX/lifetime.ll b/llvm/test/Transforms/InferAddressSpaces/NVPTX/lifetime.ll
new file mode 100644
index 0000000000000..05e46456c8bf9
--- /dev/null
+++ b/llvm/test/Transforms/InferAddressSpaces/NVPTX/lifetime.ll
@@ -0,0 +1,24 @@
+; RUN: opt -S -passes=infer-address-spaces %s | FileCheck %s
+
+target triple = "nvptx64-nvidia-cuda"
+
+define i32 @lifetime_flat_pointer() {
+; CHECK-LABEL: define i32 @lifetime_flat_pointer() {
+; CHECK-NEXT:    [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5)
+; CHECK-NEXT:    call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[ALLOCA]])
+; CHECK-NEXT:    store i32 1, ptr addrspace(5) [[ALLOCA]], align 4
+; CHECK-NEXT:    %ret = load i32, ptr addrspace(5) [[ALLOCA]], align 4
+; CHECK-NEXT:    call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[ALLOCA]])
+; CHECK-NEXT:    ret i32 %ret
+;
+  %alloca = alloca i32, align 4, addrspace(5)
+  %flat = addrspacecast ptr addrspace(5) %alloca to ptr
+  call void @llvm.lifetime.start.p0(i64 4 , ptr %flat)
+  store i32 1, ptr %flat, align 4
+  %ret = load i32, ptr %flat, align 4
+  call void @llvm.lifetime.end.p0(i64 4 , ptr %flat)
+  ret i32 %ret
+}
+
+declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture)
+declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture)

llvm/test/Transforms/InferAddressSpaces/AMDGPU/lifetime.ll

llvm/test/Transforms/InferAddressSpaces/NVPTX/lifetime.ll

arsenm

LGTM but I'd probably just delete the NVPTX tests. The first function there isn't representative IR, and the second is a no-op

arsenm · 2025-05-22T12:41:10Z

llvm/test/Transforms/InferAddressSpaces/NVPTX/lifetime.ll

+  call void @llvm.lifetime.start.p5(i64 4 , ptr %alloca)
+  store i32 1, ptr %alloca, align 4
+  %ret = load i32, ptr %alloca, align 4
+  call void @llvm.lifetime.end.p5(i64 4 , ptr %alloca)


Suggested change

call void @llvm.lifetime.start.p5(i64 4 , ptr %alloca)

store i32 1, ptr %alloca, align 4

%ret = load i32, ptr %alloca, align 4

call void @llvm.lifetime.end.p5(i64 4 , ptr %alloca)

call void @llvm.lifetime.start.p5(i64 4, ptr %alloca)

store i32 1, ptr %alloca, align 4

%ret = load i32, ptr %alloca, align 4

call void @llvm.lifetime.end.p5(i64 4, ptr %alloca)

The second one is a typo. Please check if it is needed in this scene. The following is the difference between IR before and after this PR:

%alloca = alloca i32, align 4
call void @llvm.lifetime.start.p0(i64 4 , ptr %alloca)
store i32 1, ptr %alloca, align 4
%ret = load i32, ptr %alloca, align 4
call void @llvm.lifetime.end.p0(i64 4 , ptr %alloca)
ret i32 %ret

before PR:

%alloca = alloca i32, align 4
%1 = addrspacecast ptr %alloca to ptr addrspace(5)
%2 = addrspacecast ptr addrspace(5) %1 to ptr
%3 = addrspacecast ptr addrspace(5) %1 to ptr
call void @llvm.lifetime.start.p0(i64 4, ptr %2)
store i32 1, ptr addrspace(5) %1, align 4
%ret = load i32, ptr addrspace(5) %1, align 4
call void @llvm.lifetime.end.p0(i64 4, ptr %3)
ret i32 %ret

after PR:

%alloca = alloca i32, align 4
%1 = addrspacecast ptr %alloca to ptr addrspace(5)
call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) %1)
store i32 1, ptr addrspace(5) %1, align 4
%ret = load i32, ptr addrspace(5) %1, align 4
call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) %1)
ret i32 %ret

OK, so it demonstrates a possible phase ordering with the alloca lowering PTX does, I suppose that's useful, if you adjust the test to look like this "before PR" version

Got it, done, thanks

llvm/test/Transforms/InferAddressSpaces/AMDGPU/lifetime.ll

github-actions · 2025-05-22T16:06:19Z

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[InferAddressSpaces] Handle llvm.lifetime

4175c7d

llvmbot added backend:AMDGPU backend:NVPTX llvm:transforms labels May 22, 2025

arsenm reviewed May 22, 2025

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llvm/test/Transforms/InferAddressSpaces/AMDGPU/lifetime.ll Outdated Show resolved Hide resolved

llvm/test/Transforms/InferAddressSpaces/NVPTX/lifetime.ll Show resolved Hide resolved

fixup! [InferAddressSpaces] Handle llvm.lifetime

3c4e628

arsenm approved these changes May 22, 2025

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arsenm and others added 2 commits May 22, 2025 14:42

Remove empty line

0e37754

fixup! fixup! [InferAddressSpaces] Handle llvm.lifetime

1db5ba4

arsenm approved these changes May 22, 2025

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arsenm merged commit 758fea0 into llvm:main May 22, 2025
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[InferAddressSpaces] Handle llvm.lifetime #141045

[InferAddressSpaces] Handle llvm.lifetime #141045

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[InferAddressSpaces] Handle llvm.lifetime #141045

[InferAddressSpaces] Handle llvm.lifetime #141045

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