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Bitfile versioning #18

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Merged
merged 17 commits into from
Aug 29, 2022
Merged

Bitfile versioning #18

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c174551
Add bitfile_version to FPGA class
Ajstros Aug 17, 2022
d1008b1
Add bitfile_version to .h5 header in DDR3.save_data
Ajstros Aug 17, 2022
e2a886d
Merge branch 'main' of https://github.com/Ajstros/pyripherals into bi…
Ajstros Aug 19, 2022
fd36347
Add str_bitfile_version
Ajstros Aug 19, 2022
43917b6
data_to_names accounts for bitfile version
Ajstros Aug 19, 2022
4447d24
Fix data_to_names bitfile_version default value bug
Ajstros Aug 19, 2022
48bc863
Account for KeyError when accessing BITFILE_VERSION Endpoint
Ajstros Aug 19, 2022
56e3aab
Clarify bitfile version print
Ajstros Aug 19, 2022
8879c36
Fix FIFO index and sample size in DDR3 parameters
Ajstros Aug 19, 2022
1b7d68f
Add append option to DDR3.save_data
Ajstros Aug 23, 2022
7ca046d
Fix append option
Ajstros Aug 23, 2022
cd15131
Fix append option
Ajstros Aug 23, 2022
c69c2db
Fix append option
Ajstros Aug 23, 2022
3a9061c
Add full data return to DDR3.save_data
Ajstros Aug 23, 2022
3378e0e
Return new data instead of all data
Ajstros Aug 23, 2022
75ed379
Fix new data return
Ajstros Aug 23, 2022
cdba4d7
Fix new data return
Ajstros Aug 23, 2022
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12 changes: 6 additions & 6 deletions python/src/pyripherals/peripherals/DDR3.py
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Original file line number Diff line number Diff line change
Expand Up @@ -602,7 +602,7 @@ def deswizzle(self, d, convert_twos=True):

return chan_data

def data_to_names(self, chan_data, old=False):
def data_to_names(self, chan_data, bitfile_version=self.fpga.bitfile_version):
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I'm not certain how the default parameter self.fpga.bitfile_version will behave if DDR3 is instantiated before the FPGA is initialized. The preferred usage might be that the bitfile_version is determined from the h5 file. Doing so will allow for offline data analysis to be done without an FPGA instance.

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The code has been updated, as outlined below. The idea is that we will pass in the bitfile version number from the .h5 file when we call data_to_names. This keeps data_to_names indepedent from .h5 files, so that we keep the option of reading DDR data without saving to a .h5 file open.

"""
Put deswizzled data into dictionaries with names that match with the data sources.
Complete twos complement conversion where necessary. Check timestamps for skips.
Expand All @@ -617,8 +617,8 @@ def data_to_names(self, chan_data, old=False):
----------
chan_data : dict of np.arrays
data from reading DDR (minimally processed into 2 byte containers)
old : bool
indicates if the chan data is from before the ADS channel B was repositioned to fix synchronization issues
bitfile_version : int
The bitfile version that the .h5 file which held chan_data was created with. Defaults to the bitfile version of the FPGA

Returns
-------
Expand Down Expand Up @@ -657,7 +657,7 @@ def data_to_names(self, chan_data, old=False):
# adc_data[i] = custom_signed_to_int(chan_data[i], 16)
adc_data[i] = chan_data[i]

if old:
if bitfile_version < 2: # 00.00.02 -> 2
lsb = chan_data[6][0::5].astype(np.uint64)
else:
lsb = chan_data[7][1::5].astype(np.uint64)
Expand Down Expand Up @@ -686,7 +686,7 @@ def data_to_names(self, chan_data, old=False):

ads = {}
ads['A'] = custom_signed_to_int(chan_data[7][0::5], 16)
if old:
if bitfile_version < 2: # 00.00.02 -> 2
ads['B'] = custom_signed_to_int(chan_data[7][1::5], 16)
else:
ads['B'] = custom_signed_to_int(chan_data[6][0::5], 16)
Expand Down Expand Up @@ -752,7 +752,7 @@ def save_data(self, data_dir, file_name, num_repeats=4, blk_multiples=40):
data_set = file.create_dataset("adc", (self.parameters['adc_channels'], chunk_size), maxshape=(
self.parameters['adc_channels'], None))
data_set.attrs['bitfile_version'] = self.fpga.bitfile_version

while repeat < num_repeats:
d, bytes_read_error = self.read_adc(blk_multiples)
if self.parameters['data_version'] == 'ADC_NO_TIMESTAMPS':
Expand Down