pyripherals is a Python package for communicating with peripheral electronic devices. It has a Register class to keep track of internal registers, but is most useful when used with a FrontPanel compatible Opal Kelly FPGA. With that, pyripherals makes use of the FrontPanel API for Python and Verilog to communicate more easily on common interfaces such as I2C and SPI.
- Install with pip
Note that not all of pyripherals will work with Python 3.10
pip install pyripherals
To use an FPGA and peripherals:
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Download FrontPanel from OpalKelly
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Download Registers.xlsx from the GitHub
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Create config.yaml with create_yaml and edit fields as needed
>>> from pyripherals.utils import create_yaml
>>> create_yaml()
YAML created at C:/Users/username/.pyripheralsSee Installation Guide for more information.
Documentation is hosted on Read the Docs.
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The Verilog I2C controller is from OpalKelly OpalKelly I2CController (MIT License).
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The Verilog AD7961 controller is from Analog Devices and is free to use / redistribute as long as its used with Analog Devices parts (which must be the case since it does not work if connected to other parts). The Verilog is available within the EVAL-AD7960 evaluation kit software
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The Verilog SPI Controller is from OpenCores.org and is authored by Simon Srot (GPL 2.1 or later license).
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The Verilog wishbone master is written by Dan Gisselquist, Gisselquist Technology LLC. (LGPL, v3)
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The DDR user interface (ddr_test.v) started with the OpalKelly DDR example provided in the FrontPanel example RAMTester and was significantly modified to support two ports.
- numpy
- numfi
- matplotlib
- pandas
- openpyxl
- h5py
- pyyaml
- scipy
We have targeted and tested with the XEM7310-A75 module (Xilinx Artix-7). We have not tested but anticipate reasonable portability to other USB 3 OpalKelly modules:
- XEM7310MT
- XEM7320
- XEM7305
- XEM7360
This is the block diagram of the top_level_module.bit bitfile
