Figure out why PAR occasionally takes 2.5 hours when it normally only takes 30 minutes #72
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Since setting PYTHONHASHSEED=0 it seems like this is reasonably reproducible. The following build at https://travis-ci.org/timvideos/HDMI2USB-misoc-firmware/jobs/83922006 is reliably hitting this case. |
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It should no longer happen since buf_fifo of the jpeg encoder is refactored (#53) and was the one using too much ressources. |
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This issue continues to occur after the buf_fifo has been removed (but less frequently). |
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Aug 28, 2018
* edid-decode changed from dcc8b83 to b2da151
* b2da151 - edid-decode: add --extract and --check options <Hans Verkuil>
* e9ffafc - edid-decode: add options and new output formats <Hans Verkuil>
* ab18bef - edid-decode: add HDMI Forum VSDB fields for HDMI 2.1b <Hans Verkuil>
* 8c81ccf - Add Samsung UE49KS8005 EDID <Hans Verkuil>
* 7d8f41f - edid-decode: simplify data block parsing <Hans Verkuil>
* eee377b - edid-decode: add support for QuantumData 980 EDID file format <Hans Verkuil>
* 4437dd9 - edid-decode: use const for unsigned char pointers to the EDID <Hans Verkuil>
* 3b26b8a - edid-decode: fix wrong sample rate unit <Hans Verkuil>
* 9cb3744 - edid-decode: fix spurious warning about string termination <Hans Verkuil>
* bc1e846 - edid-decode: reformat to linux kernel coding style <Hans Verkuil>
* 7684918 - edid-decode: README: updates <Hans Verkuil>
* 9e59ba9 - edid-decode: update links, add README <Hans Verkuil>
* 0a454bc - makefile: also honor LDFLAGS <Adam Jackson>
* litedram changed from 45da365 to 7a5ac75
* 7a5ac75 - test/test_axi: improve test_axi2native <Florent Kermarrec>
* d53832d - frontend/axi: split LiteDRAMAXI2Native (write path and read path) <Florent Kermarrec>
* c846b8b - frontend/axi: add burst support (fixed/incr) <Florent Kermarrec>
* 3fa77c8 - phy/s6ddrphy: use cwl only for DDR3 <Florent Kermarrec>
* d9b5bb7 - frontend/bist: support axi with addressing in bytes <Florent Kermarrec>
* 1370617 - frontend/axi: addressing in bytes not internal dwords <Florent Kermarrec>
* 06f841d - sdram_init: compute write recovery cycles (we were using max value) <Florent Kermarrec>
* 53c75f5 - phy/s7ddrphy: add dqs preamble/postamble <Florent Kermarrec>
* 1c083ea - sdram_init: split init_sequence generation and header geneneration and add .py header genration <Florent Kermarrec>
* d7d60cf - Merge branch 'master' of http://github.com/enjoy-digital/litedram <Florent Kermarrec>
|\
| * cd330b4 - Merge pull request #28 from AlphamaxMedia/refactor-master <enjoy-digital>
| |\
| | * 818c678 - update module settings to reflect latest changes <bunnie>
| | * c9b8db5 - i think there's a missing "self" in the params <bunnie>
* | | ae6f10a - sdram_init: use 60ohm as rtt_wr default value <Florent Kermarrec>
|/ /
* | 522cbc9 - frontend: add AXI support for dma and bist <Florent Kermarrec>
* | 5715734 - frontend: add initial AXI support <Florent Kermarrec>
* | 97349bc - frontend: rename bridge to wishbone and LiteDRAMWishboneBridge to LiteDRAMWishbone2Native <Florent Kermarrec>
* | 2b20c11 - add LiteDRAMNativePort to prepare for AXI, change some internals and API of get_port but keep retro-compatibility - LiteDRAMPort -> LiteDRAMNativePort - aw -> address_width - dw -> data_width - cd -> clock_domain <Florent Kermarrec>
|/
* 0b6e21a - improve ddr3 electrical settings <Florent Kermarrec>
* 697eaaf - add board tuning parameters <bunnie>
* 9a57c4e - phy/s7ddrphy: add DDR3-800 timings <Florent Kermarrec>
* 9401b92 - move sdram_init to litedram <Florent Kermarrec>
* 209dc0d - frontend/bist: add dynamic random data and addressing <Florent Kermarrec>
* b13962c - core/multiplexer: fix 1:1 <Florent Kermarrec>
* a215ac7 - core/multiplexer: fix count signal width (when max<2) <Florent Kermarrec>
* ad8438f - core/controller: enable auto_precharge by default <Florent Kermarrec>
* bba4913 - core/bankmachine: fix auto_precharge (OR on the two buffers for req.lock), don't need to wait for precharge timer to issue auto-precharge <Florent Kermarrec>
* 2e362ee - core/bankmachine: add auto_precharge setting to enable/disable auto_precharge mode (disabled by defaut) <Florent Kermarrec>
* 6d23421 - core/bankmachine: rename cmd_bufferPre to cmd_buffer_lookahead <Florent Kermarrec>
* 23358b5 - core/multiplexer: use self.submodules for timing controllers, fix tFAW count <Florent Kermarrec>
* db4ec67 - Merge pull request #24 from JohnSully/AutoPrecharge <enjoy-digital>
|\
| * 627cccd - Fix tCCD timing which watched the wrong command <>
| * 16a852b - Revert "core/refresher: synchronize valid" <>
| * a4be642 - Fix multiple timings ignored <>
| * 771ccfd - Merge branch 'master' of https://github.com/enjoy-digital/litedram into AutoPrecharge <>
| |\
| |/
|/|
* | 6620a91 - core/refresher: synchronize valid <Florent Kermarrec>
* | b2f1f29 - core/bankmachine: update comments <Florent Kermarrec>
* | c1b1b07 - core/multiplexer: synchronize ready on tXXDController and tFAWcontroller to improve timings <Florent Kermarrec>
* | 147466b - multiplexer: create timing controllers module and simplify <Florent Kermarrec>
* | eeb57ad - Merge pull request #23 from JohnSully/outoforder <enjoy-digital>
|\ \
| | * 3206985 - When auto-precharging assert track_close <>
| | * 74279ea - Enable auto-precharge <>
| |/
| * 03a2ad6 - Ensure out of order is on a per-bank basis <>
| * 86b3e2d - Add reorder flag to the crossbar <>
| * 77c513d - Merge upstream. UNTESTED <>
| |\
| |/
|/|
* | c28a754 - test: update <Florent Kermarrec>
* | f7f8452 - core: make rdata_bank optional (break cdc when enabled), fix some usecases <Florent Kermarrec>
* | 873b970 - frontend: avoid breaking api with last rbank change (use bankbits_max), some cleanup <Florent Kermarrec>
* | 26f3f01 - Merge pull request #21 from JohnSully/outoforder <enjoy-digital>
|\ \
* \ \ 74c3c09 - Merge pull request #20 from bunnie/400mhz-pr <enjoy-digital>
|\ \ \
| * | | 4823058 - Adding comment to iodelay_tap_average dictionary. <Tim Ansell>
| * | | d986b60 - add 400MHz tap setting (valid for -3 and -2/2E speed grades) <bunnie>
* | | | e02a251 - core: make tRRD definition optional and some cosmetic changes <Florent Kermarrec>
* | | | 5d74eb2 - Merge pull request #19 from JohnSully/timing <enjoy-digital>
|\ \ \ \
| |/ / /
|/| | |
| | | * 8266a6e - Prevent compilation failures when tRRD == 0 <>
| | | * ed4be0b - Add write bank to out of order interface <>
| | |/
| | * bfa1d6a - remove debug prints <>
| | * 2fa2a6d - Initial implementation of out of order controller <>
| | * f1fea6d - Correct tWTR timing: 1) timing starts after the completion of the write burst, 2) We don't need to wait on switches if a write hasn't taken place recently <>
| |/
| * eb3f4a0 - fix CAS to CAS timings (needs to account for multiple banks) <>
| * f0f5e60 - Add tRRD timing checks, and fix tFAW so it considers all banks <>
|/
* f0f067f - phy/s7ddrphy: add assert to make sure cmd/dat phases are not identical <Florent Kermarrec>
* f560b9c - core/bankmachine: remove auto-prechage since introducing a regression, we'll need to do more simulation before integrating <Florent Kermarrec>
* 2736ebc - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
* e830526 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
* 6d96bcc - core/bankmachine: fix cas_count size when tccd == 1 <Florent Kermarrec>
* f4ad65e - core/controller: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) <Florent Kermarrec>
* eee89d4 - phy/s7ddrphy: add ddr2 support <Florent Kermarrec>
* c9f2e30 - core/controller: add simulation workaround for 1:2 ddr3 phy <Florent Kermarrec>
* bd09471 - phy/s7ddrphy: add 1:2 frequency ratio support (BC4 mode for now) <Florent Kermarrec>
* dec5378 - core/bankmachine: add CAS to CAS support (tCCD) <Florent Kermarrec>
* 5bc3575 - modules: add retro-compat on MT41J256M16 <Florent Kermarrec>
* c4dad24 - modules: add description, add speedgrade support and improve tWTR/tFAW definition (in ck, ns or greater of ck/ns) <Florent Kermarrec>
* 370b05e - core/bankmachine: add Four Activate Window support (tFAW) <Florent Kermarrec>
* d0ff536 - phy/s7ddrphy: add specific bitslip reset <Florent Kermarrec>
* 8ba7fca - core/bankmachine: simplify row change detection for auto precharge <Florent Kermarrec>
* 3255a33 - core/bankmachine: remove specific case for small cmd_buffer_depth <Florent Kermarrec>
* d150e3b - Merge pull request #12 from JohnSully/master <enjoy-digital>
|\
| * 6b0d5ce - Prevent spurious precharge all commands caused by leaving A10 asserted during precharge <>
| * d0fcfb1 - Auto-precharge now only fires when it needs to <>
* | 82b7199 - modules: fix tWTR for DDR3 modules (expressed in sys_clk not ns) <Florent Kermarrec>
* | f4b92b6 - phy/s7ddrphy: add nphases parameter to get functions <Florent Kermarrec>
* | d7d5d4a - phy/s7ddrphy: add iodelay_clk_freq parameter <Florent Kermarrec>
* | f47ddb3 - phy/s7ddrphy: add get_cl_cw function <Florent Kermarrec>
* | d9da7c5 - phy/s7ddrphy: compute phy settings automatically (based on tck) and add DDR3-1066/1333/1600 support. <Florent Kermarrec>
* | ba16ebf - phy: add common Series7 PHY (Artix7, Kintex7 & Virtex7) with or without ODELAY. Keep backward compatibility on imports. <Florent Kermarrec>
* | 2bd7707 - modules: add MT18KSF1G72HZ_1G6 <Florent Kermarrec>
|/
* c238149 - phy/kusddrphy: follow more Xilinx recommandations <Florent Kermarrec>
* liteeth changed from 33afda7 to 24b0d2b
* 24b0d2b - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
* 4edba99 - phy: remove s6rgmii (not working correctly). <Florent Kermarrec>
* 6b872fd - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
* 40d91f0 - phy: use rx_dv instead of dv <Florent Kermarrec>
* ba2fdc5 - README: add 1000BaseX phy <Florent Kermarrec>
* a2dbdd6 - phy: add a7_1000basex phy (from misoc) <Florent Kermarrec>
* 95849a0 - core/icmp: use buffered=True on buffer to allow tools to use block rams <Florent Kermarrec>
* litepcie changed from 8bc328f to a97a691
* a97a691 - example_designs: update/fix test_regs.py <Florent Kermarrec>
* d8e602c - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
* 0ac08e5 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
* cf0a3e5 - phy/kintex7: fix/update <Florent Kermarrec>
* 96309fc - core/msi: add transmit_interval parameter to avoid continous retransmission (causing issue with some configurations) <Florent Kermarrec>
* bb29b81 - core/tlp/reordering: use buffered=True on tag_buffer fifo <Florent Kermarrec>
* 418e980 - frontend/wishbone: add shadow_base parameter <Florent Kermarrec>
* 3df4217 - test/test_dma: test both 64b and 128b datapaths and fix writer <Florent Kermarrec>
* 29a7d16 - test/test_wishbone: test both 64b and 128b datapaths <Florent Kermarrec>
* 08a8daf - phy/s7pciephy: last is indicated in tuser (and not tlast) for 128 bits datapath <Florent Kermarrec>
* a20e71b - core/tlp/packetizer/depacketizer: fixes for 128 bits datapath <Florent Kermarrec>
* 93233fe - frontend/dma: cleanup control bits <Florent Kermarrec>
* 0540a88 - frontend/dma/writer: avoid stalling pipeline when not enabled <Florent Kermarrec>
* litesata changed from a559afb to 002cd25
* 002cd25 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
* 73cb6fa - example_designs: update <Florent Kermarrec>
* fd5b38e - examples_designs/platforms: add genesys2 <Florent Kermarrec>
* 236522b - example_designs/targets/bist: allow cpu_reset with both polarity <Florent Kermarrec>
* 8bdc28e - Merge pull request #14 from felixheld/crc <enjoy-digital>
|\
| * 7f61316 - core/link.py: make CRC calculation more pythonic <Felix Held>
| * e497f33 - core/link.py: clarify comments in CRC implementation <Felix Held>
* ec06424 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
* litescope changed from 9d5e605 to f26e36e
* f26e36e - Merge pull request #11 from xobs/add-trigger-depth <enjoy-digital>
|\
| * 71ffaa7 - add trigger depth option <bunnie>
|/
* bfd06f8 - core: add FSM support (and example) <Florent Kermarrec>
* 2ca58e4 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
* cd63a43 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
* f03345d - software/driver/analyzer: add get_instant_value to get instant value of one signal <Florent Kermarrec>
* af5bfd1 - software/driver/analyzer: add assertions <Florent Kermarrec>
* 3efaefa - example_designs: typo <Florent Kermarrec>
* d919f90 - core: use bits_for(n) instead of max=n on Mux (fix case with only one group of signals) <Florent Kermarrec>
* 6289e81 - example_designs: demonstrate new features <Florent Kermarrec>
* e92f0b7 - example_designs/test: cleanup and simplify <Florent Kermarrec>
* 2233bc2 - core: another cleanup/simplify pass <Florent Kermarrec>
* a269e67 - software: add rising/falling edge support <Florent Kermarrec>
* 65b7f08 - core: add full flag for trigger memory <Florent Kermarrec>
* c0bab06 - core: add sequential-triggering and simplify control <Florent Kermarrec>
* 26a8b89 - example_designs: update <Florent Kermarrec>
* 8d4c1dd - core: simplify and run storage in "scope" clock domain to get rid of cd_ratio. <Florent Kermarrec>
* liteusb changed from 23d6a68 to e841c56
* e841c56 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
* 7da831d - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
* litevideo changed from 9b4169d to 7b4240f
* 7b4240f - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
* c39517a - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
* cb8cf59 - Merge pull request #19 from bunnie/terc4-data <enjoy-digital>
* c704235 - additional debugging on capture <bunnie>
* eab7078 - add data decoding to Terc4 decoder <bunnie>
* eb263a8 - add ability to invert the HPD input <bunnie>
* 7189562 - fix a default edid that works better with rpis <bunnie>
* 33ed07d - currently commented, but the vestiges of introducing SS clocking <bunnie>
* 49adfb4 - change the default edid to one that advertises a proper 1080p mode <bunnie>
* 19437d0 - add dvimode/hdmimode setting bit for DE detection <bunnie>
* 449d339 - add decoding of terc4 islands, proper DE extraction on HDMI <bunnie>
* 447726f - add RGB input mode support to hdmi in <bunnie>
* f5842bc - add some code to allow frame start offset trimming for genlock <bunnie>
* 12aa4f9 - clarify the self vs local signal settings for easier probing <bunnie>
* 9b3c93e - move BUFR->BUFG <bunnie>
* 166dc57 - fix typo on naming <bunnie>
* 33f8833 - change the genlock method from pulse to wholesale signal change <bunnie>
* 784cc8c - changes needed for a basic genlock <bunnie>
* litex changed from v0.1-319-gb7f7c8d1 to v0.1-423-g7a14b75c
* 7a14b75c - Merge pull request #93 from phlipped/master <Tim Ansell>
|\
| * 8b51c445 - Fix URL for liteUSB <phlipped>
|/
* 0074bb88 - Merge pull request #91 from cr1901/ignore-fix <Tim Ansell>
|\
| * dd480eb7 - .gitignore: litex/build contains valid source, so exclude from .gitignore. <William D. Jones>
* | ff908e40 - Merge pull request #92 from cr1901/l2-gate <Tim Ansell>
|\ \
| * | 3146109a - software/bios: Gate flush_l2_cache() if L2 Cache isn't present. <William D. Jones>
| |/
* | 759e7d4d - bios/sdram: improve/simplify read window selection <Florent Kermarrec>
* | 09776b77 - sim: run as root only when needed (ethernet module present) <Florent Kermarrec>
* | 06e835a3 - builder: change call to get_sdram_phy_c_header and also pass timing_settings <Florent Kermarrec>
* | ee26f8c5 - soc_sdram: cosmetic <Florent Kermarrec>
* | 2db5424a - soc_sdram: vivado is now able to implement the l2_cache correctly (tested with vivado 2017.2 and >) <Florent Kermarrec>
* | 45e9a42c - soc_core: add cpu_endianness <Florent Kermarrec>
* | 3877d0f1 - builder: get_sdram_phy_header renamed to get_sdram_phy_c_header <Florent Kermarrec>
* | c64e44ef - soc_sdram: use new LiteDRAMWishbone2Native and port.data_width <Florent Kermarrec>
* | 2eeccc50 - vexriscv: update <Florent Kermarrec>
* | eecc6f68 - soc/integration: move sdram_init to litedram <Florent Kermarrec>
|/
* 077f9391 - Vexriscv: update csr-defs.h <Florent Kermarrec>
* 4225c3b8 - update Vexriscv <Florent Kermarrec>
* 95479385 - bios/sdram: changes to ease manual read window selection <Florent Kermarrec>
* a760322f - litex_server: allow multiple clients to connect to the same server <Florent Kermarrec>
* 8a69a47e - cpu/lm32: add minimal variant with no i/d cache, pipelined barrel shifter and multiplier (useful to build SoC on small FPGAs like ice40) <Florent Kermarrec>
* cb5b4ac4 - bios/boot: flush all caches before running from ram <Florent Kermarrec>
* 650ac186 - sim/verilator: catch ctrl-c on exit and revert default termios settings <Florent Kermarrec>
* 0831ad54 - cpu_interace: use riscv64-unknown-elf if available else riscv32-unknown-elf <Florent Kermarrec>
* 1610a7f3 - bios/sdram: fix read_level_scan result <Florent Kermarrec>
* e07ca057 - Merge pull request #86 from pgielda/patch-1 <enjoy-digital>
|\
| * 3c7890cd - Fix generating csr.csv file <Peter Gielda>
|/
* 9fa234da - soc/intergration/cpu_interface: typo <Florent Kermarrec>
* 22f645ad - bios/main: use edata instead of erodata <Florent Kermarrec>
* 580efecc - picorv32: add reset signal <Florent Kermarrec>
* 0429ee9f - soc/software/bios: add reboot command <Florent Kermarrec>
* da751598 - soc/integration/soc_core: add Controller with reset, scratch and bus_errors registers <Florent Kermarrec>
* 8ba56252 - soc/interconnect/wishbone: add Timeout to avoid stalling bus when not responding and generate error. <Florent Kermarrec>
* c0989f65 - soc/cores/cpu: add reset signal <Florent Kermarrec>
* 380f8b96 - Merge pull request #81 from xobs/vexriscv-to-wishbone <enjoy-digital>
|\
| * fb145dac - tools: remove vexriscv_debug <Sean Cross>
| * f17b8324 - vexriscv: reset wishbone bus on CPU reset <Sean Cross>
| * c87ca4f1 - vexriscv: put debug bus directly on wishbone bus <Sean Cross>
|/
* 20d6fcac - add litex_setup script to clone and install Migen, LiteX and LiteX's cores <Florent Kermarrec>
* 8a311bf4 - build/generic_platform: use list for sources instead of set <Florent Kermarrec>
* df7e5dbc - bios/sdram: add ERR_DDRPH_BITSLIP constant and some cleanup <Florent Kermarrec>
* 1564b440 - soc/integration/soc_sdram: add assertion on csr_data_width since BIOS only support SDRAM initialization for csr_data_width=8 <Florent Kermarrec>
* ae62fe07 - setup.pu: fix exclude <Florent Kermarrec>
* c314193c - boards/plarforms/genesys2: replace user_dip_sw with user_sw <Florent Kermarrec>
* 10dd55fd - boards/platforms/genesys2: add minimum HPC connectors to be able to test SATA, add programmer parameter <Florent Kermarrec>
* b19844d1 - setup.py: exclude test, sim, doc directories <Florent Kermarrec>
* 85308672 - software/bios/linker: revert data section since required by RISC-V compiler <Florent Kermarrec>
* 55dd58b0 - Merge pull request #80 from xobs/fix-vexriscv-csr-read <enjoy-digital>
|\
| * 41a9e7d9 - vexriscv_debug: use csr read()/write() accessors <Sean Cross>
* | 7ecdcaca - soc/integration/sdram_init: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) <Florent Kermarrec>
* | a4caa896 - targets/nexys_video: remove read leveling constants (now automatic) <Florent Kermarrec>
* | d8250041 - targets/nexys4ddr: s7ddrphy now supports ddr2, working <Florent Kermarrec>
* | 4f1274e6 - bios/sdram: improve bitslip selection when window can't be optimal (not enough taps for a full window) <Florent Kermarrec>
* | 7dbd85a8 - soc/cores/uart: rename UARTMultiplexer to RS232PHYMultiplexer. UARTMultiplexer now acts on serial signals (tx/rx) <Florent Kermarrec>
* | ef1c7784 - soc_core: add csr_expose parameter to be able to expose csr bus (useful when design is integrated in another) <Florent Kermarrec>
|/
* f9104b20 - bios/sdram: improve read leveling (artix7 read-leveling is now done automatically at startup) <Florent Kermarrec>
* c84e189d - bios/sdram: fix compilation with no write leveling <Florent Kermarrec>
* b062d4dd - Merge pull request #79 from xobs/fix-vexriscv-data-read <enjoy-digital>
|\
| * be8eb5ff - vexriscv: debug: fix reading DATA register <Sean Cross>
|/
* e35be26e - Merge pull request #78 from xobs/vexriscv_debug_bridge <enjoy-digital>
|\
| * 6bc9265c - setup: add vexriscv_debug to list of entrypoints <Sean Cross>
| * 45a649be - tools: vexriscv_debug: add debug bridge <Sean Cross>
|/
* c821a0fe - cores/cpu/vexriscv: create variants: None and "debug", some cleanup <Florent Kermarrec>
* 59fa7159 - core/cpu/vexriscv/core: improve indentation <Florent Kermarrec>
* 6068f6ce - Merge pull request #77 from xobs/debug-vexriscv-enjoy <enjoy-digital>
|\
| * 32d5a751 - soc_core: uart: add a reset line to the UART <Sean Cross>
| * 1ef127e0 - soc: integration: use the new cpu_debugging flag for vexriscv <Sean Cross>
| * e7c762c8 - soc: vexriscv: add cpu debug support <Sean Cross>
| * 2024542a - vexriscv: verilog: pull debug-enabled verilog <Sean Cross>
* | 11e84915 - platforms/arty_s7: keep up to date with Migen <Florent Kermarrec>
* | d35dc5cd - platforms/arty: merge with Migen <Florent Kermarrec>
|/
* fa021566 - platforms/kc705: keep up to date with Migen <Florent Kermarrec>
* b9f3b49c - platforms/de0nano: keep up to date with Migen <Florent Kermarrec>
* 1628c36a - README/boards: add precision on Migen's platforms <Florent Kermarrec>
* df99cc66 - bios/sdram: also check for last read of scan to choose optimal window <Florent Kermarrec>
* 8ce7fcb2 - bios/main: add cpu frequency to banner <Florent Kermarrec>
* 477d2249 - bios/sdram: check for optimal read window before doing read leveling, increment bitslip if not optimal. <Florent Kermarrec>
* 9e737d3c - soc/cores/code_8b10b: update (from misoc) <Florent Kermarrec>
* d58eb4ec - bios/sdram: use new phy, improve scan, allow disabling high skew <Florent Kermarrec>
* 692cb142 - software/bios: fix picorv32 boot_helper <Florent Kermarrec>
* b5ee110e - bios/sdram: add write/read leveling scans <Florent Kermarrec>
* 34b2bd0c - boards: add genesys2 (platform with clk/serial/dram/ethernet + target) <Florent Kermarrec>
* 8edc659d - soc_core: remove assert on interrupt (added to catch design issues, but too restrictive for some usecases) <Florent Kermarrec>
* 2c13b701 - soc/integration/cpu_interface: add shadow_base parameter <Florent Kermarrec>
* 78639fa9 - Merge pull request #75 from xobs/bios-windows-build <enjoy-digital>
|\
| * 74449929 - soc: bios: fix windows build <Sean Cross>
|/
* 18f86881 - targets: change a7/k7ddrphy imports to s7ddrphy <Florent Kermarrec>
* 3e723d15 - soc/cores/cpu: add add_sources static method <Florent Kermarrec>
* c534250c - Merge pull request #72 from bunnie/fix_riscv_boothelper <enjoy-digital>
|\
| * 7353197e - fix the vexriscv boot helper <bunnie>
|/
* 5ab4282e - Merge pull request #71 from DeanoC/master <enjoy-digital>
|\
| * 34a93034 - Fix for missing connectors for arty boards <Deano Calver>
|/
* e7d1683e - litex_term: cleanup getkey and revert default settings on KeyboardInterrupt <Florent Kermarrec>
* 06162b61 - README: add list of supported CPUs/Cores and add link to tutorials <Florent Kermarrec>
* 6854c7f5 - soc/integration/cpu_interface: use riscv64 toolchain instead of riscv32 (prebuild toolchain for windows can be found at http://gnutoolchains.com/) <Florent Kermarrec>
* 66229c8c - add VexRiscv support (imported/adapted from misoc) <Dolu1990>
* f60da4a5 - add VexRiscv submodule <Florent Kermarrec>
* d149f386 - allow multiple riscv32 softcores (use picorv32 cpu_type instead of riscv32) <Florent Kermarrec>
* c3652935 - build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation) <Florent Kermarrec>
* 121eaba7 - soc/intergration/soc_core: don't delete uart/timer0 interrupts <Florent Kermarrec>
* 39ffa532 - xilinx/programmer: fix programmer <Florent Kermarrec>
* c001b8ea - build/xilinx/vivado: add vivado ip support <Florent Kermarrec>
* 43f8c230 - soc_core: uncomment uart interrupt deletion <Florent Kermarrec>
* d7c74746 - gen/sim: fix import to use litex simulator instead of migen simulator <Florent Kermarrec>
* migen changed from 0.6.dev-99-g881741b to 0.6.dev-162-ga6082d5
* a6082d5 - added support for qm_xc6slx16_sdram <Daniel Kucera>
* 2d37c78 - add indexed part select support <Robin Ole Heinemann>
* 5fe1bfe - build/platforms: Add tinyfpga_a platform. (#111) <William D. Jones>
* 307e752 - fhdl.specials: add reset_i argument to TSTriple. <whitequark>
* 18274c3 - build.lattice: fix IcestormTristate override for 1-bit signals. <whitequark>
* e07c1c5 - build.lattice: add IcestormTristate override. <whitequark>
* 0509a7b - fhdl.verilog: make convert() idempotent. <whitequark>
* 5dd4efa - genlib.fifo: add read() and write() methods, for simulation. <whitequark>
* 4e4833d - sayma_amc: AMC_MASTER_AUX_CLK is in a 3.3V bank, needs LVDS_25, cannot use termination <Sebastien Bourdeauducq>
* 47f4c59 - typo <Sebastien Bourdeauducq>
* 870935d - sayma_amc: add AMC_MASTER_AUX_CLK <Sebastien Bourdeauducq>
* bef9dea - platform: support recursive connector pins <Sebastien Bourdeauducq>
* cb171af - platform: support adding connectors <Sebastien Bourdeauducq>
* 26d77fe - xilinx/ise: Add Cygwin path to Windows conversion in xst files (#88) <William D. Jones>
* 1ec3ea9 - sayma_rtm: add hmc7043_gpo <Sebastien Bourdeauducq>
* b515b0e - platforms/arty_a7: merge with LiteX's platform, remove the FIXMEs <Florent Kermarrec>
* 9d3db58 - Sayma AMC: add SYSCLK1_300 <Thomas Harty>
* daf6f5d - sayma: add adc_sysref pins <Sebastien Bourdeauducq>
* dcfec40 - sayma_amc: fix raw RTM GTH pair polarities <Sebastien Bourdeauducq>
* 7823da4 - sayma_amc: add raw RTM GTH pairs <Sebastien Bourdeauducq>
* df0ce4a - Update version in setup.py. <whitequark>
* e4e92dc - Fixed case of xadc to match kc705. <Caleb Jamison>
* 84186ca - Changed ck_io to name pins, add xadc. <Caleb Jamison>
* c2480c9 - Removed _ from spiflash_4x <Caleb Jamison>
* fd7ce92 - Moved pmods to _connectors, removed _1x from spiflash <Caleb Jamison>
* 2896306 - Changed spiflash_1x to spiflash in _io list. <Caleb Jamison>
* ede1c9e - Add _connectors to constructor <Caleb Jamison>
* 20d28d4 - Removed extra field from _connector list <Caleb Jamison>
* 02e80df - Add chipkit io to _connector list <Caleb Jamison>
* 1eeb38d - Fixed missing parens, extra spaces <Caleb Jamison>
* 0dd85cd - Split pmods to _connectors, checked against litex <Caleb Jamison>
* 04a9914 - Arty A7 platform <Caleb Jamison>
* 07c46f5 - Support for AFC 3v1 <Mikołaj Sowiński>
* 9929b23 - sayma_amc: fix 19e82b7 syntax <Robert Jördens>
* 19e82b7 - sayma_amc: diff term lvds inputs <Robert Jördens>
* a51a5f6 - sayma: use LVCMOS18 for serwb <Sebastien Bourdeauducq>
* 34a3c62 - sayma_rtm: LVDS_18 is called LVDS <Sebastien Bourdeauducq>
* e5cabe1 - sayma_rtm: fix I/O bank voltages <Sebastien Bourdeauducq>
* 5947224 - sayma_rtm: add ref_lo_clk_sel <Robert Jördens>
* 4cb07f1 - bitcontainer: slices are unsigned <Robert Jördens>
* ca28f4e - platforms/sayma_amc/serwb: use DIFF_TERM_ADV=TERM_100 <Florent Kermarrec>
* 6425844 - revert genlib/cdc: add optional master parameter to ElasticBuffer to allow sharing write reset between ElasticBuffers <Florent Kermarrec>
* 33bb06a - genlib/cdc: add optional master parameter to ElasticBuffer to allow sharing write reset between ElasticBuffers <Florent Kermarrec>
* 48f2b92 - doc/fhdl: use correct syntax for code block. <whitequark>
* e66f2df - Fix documentation link in README. <whitequark>
* 2423404 - fhdl.verilog: fix nondeterminism in _printcomb. <whitequark>
* 0aa76fa - build/platforms: Add Arty S7 platform. <William D. Jones>
* 19ca7d8 - platforms/tinyfpga_b: Add default serial mapping. <William D. Jones>
* cba5bea - sayma_amc/rtm: use DIFF_TERM=TRUE on serwb lvds inputs <Florent Kermarrec>
* 9bc084a - Update .gitignore. <whitequark>
* d46aa13 - fhdl.verilog: do not initialize combinatorial regs. <whitequark>
* 02bccef - Fix breakage introduced in 2220222. <whitequark>
* d667233 - LatticeIceStormToolchain: pass --no-promote-globals to arachne-pnr. <whitequark>
* 2220222 - genlib.cdc.MultiReg: allow specifying reset value for registers. <whitequark>
* 5c2c144 - sayma_rtm: enable OVERTEMPPOWERDOWN and use options from artiq <Robert Jordens>
* 24d0e95 - samya_amc: enable OVERTEMPPOWERDOWN <Robert Jordens>
* a32a0f7 - kasli: enable OVERTEMPPOWERDOWN <Robert Jordens>
* 81d0be3 - DDROutputImplS7: make it SAME_EDGE and fix it <Robert Jordens>
* 4039322 - kasli: mark negative polarity of mod_present on v1.1 <Sebastien Bourdeauducq>
* b50e224 - Add DE0-Nano-SoC (aka Atlas-SoC) platform (#96) <Adam Greig>
* c14a1e4 - Add MyStorm BlackIce I and II platforms (#95) <Adam Greig>
* f4180e9 - vivado: print short timing info after phys_opt_design <Sebastien Bourdeauducq>
* c65a2f3 - vivado: run phys_opt_design after routing <Sebastien Bourdeauducq>
Full submodule status
--
b2da1516df3cc2756bfe8d1fa06d7bf2562ba1f4 edid-decode (remotes/origin/HEAD)
a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
7a5ac75e2295dcf15f83df966244f30154a8f662 litedram (remotes/origin/HEAD)
24b0d2b8c2cfcf96a8c6cb56ec01af9a56952aad liteeth (remotes/origin/HEAD)
a97a6910cbebfb4c068a178139df7b9a9c72168f litepcie (remotes/origin/HEAD)
002cd25e7fd2a60b4dcf1ce829731b9cf5c2f744 litesata (remotes/origin/HEAD)
f26e36ef23170002af8ab1461ba39209e531b6cb litescope (remotes/origin/HEAD)
e841c5646c17ecbf07642c69c16c6c7c45e55475 liteusb (remotes/origin/HEAD)
7b4240f9b3d6b7e69e5fe9dbaf50e117bd0ca704 litevideo (remotes/origin/HEAD)
7a14b75cd676e9328063abc1fcdc6fcd4fc6c5ef litex (v0.1-423-g7a14b75c)
a6082d56ccc615229bd3b5205f5b7207c14dca01 migen (0.6.dev-162-ga6082d5)
mithro
added a commit
that referenced
this issue
Sep 30, 2018
scripts: Improve download-prebuilt script.
Merged
mithro
added a commit
that referenced
this issue
Feb 14, 2019
* litedram changed from 906edf1 to d89b171
* d89b171 - modules/mt40a1g8: use _L (long) timings <Florent Kermarrec>
* 2d4fdd1 - litedram/sdram_init/ddr4: disable data mask (not required) <Florent Kermarrec>
* 0b49cbb - Merge pull request #74 from softerhardware/master <enjoy-digital>
|\
| * d65377f - Update to MT40A1G8 that Phillip was successful with <Steve Haynal - VSD Engineering>
* | f207454 - sdram_init/ddr4: set data mask enable bit <Florent Kermarrec>
* | 6d09a47 - Merge pull request #73 from softerhardware/master <enjoy-digital>
|\ \
| |/
| * 8e6ad4c - Additional DDR3 and DDR4 SDRAMModules <Steve Haynal - VSD Engineering>
* | 92df55f - travis: change tests order, comment test_examples for now (need to install the CPU toolchain to travis) <Florent Kermarrec>
|/
* 2d4b5ba - core/crossbar: cosmetic <Florent Kermarrec>
* 429d3a8 - test/common: set rdata_valid_rand_level default value to 0 <Florent Kermarrec>
* 9ddb3e2 - travis: set python version to 3.6 <Florent Kermarrec>
* cc38804 - Merge pull request #72 from EwoutH/master <enjoy-digital>
|\
| * 8e01cba - Add Travis CI (#1) <Ewout ter Hoeven>
|/
* 031746a - frontend/bist: fix for data_width < 31 (16 bits SDRAMs) <Florent Kermarrec>
* b4c552a - core/multiplexer: fix command steering for nphases=1 (SDRAM), thanks jfng <Florent Kermarrec>
* 224a423 - common: allow setting electrical settings with DDR4 <Florent Kermarrec>
* fc3a192 - phy/gensdrphy: make CAS latency configurable <Florent Kermarrec>
* b4ee95c - sdram_init: generate ddrx_mr1 only if mr1 is not None <Florent Kermarrec>
* 2483d25 - test/test_ecc: update <Florent Kermarrec>
* 6757a14 - frontend/ecc: add error injection capability <Florent Kermarrec>
* 7eee80d - frontend/ecc: add description, rename dec signal to ded <Florent Kermarrec>
* 14c6062 - core/crossbar: remove "ROW_COL_BANK" address_mapping (need to be simulated) <Florent Kermarrec>
* 180b3d2 - modules: adjust MT48LC16M16 timings <Florent Kermarrec>
* liteeth changed from d7fdcbb to 77fa4bf
* 77fa4bf - phy: add Kintex7 1000BaseX PHY <Florent Kermarrec>
* c2d8a46 - phy: add Kintex Ultrascale PHY (copyright M-Labs Ltd) <Florent Kermarrec>
* litepcie changed from b29c3a0 to 3804c49
* 3804c49 - frontend/dma: use max_request_size constant for DMAReader <Florent Kermarrec>
* 3c4eb61 - core/msi: don't wait retransmit timer when irq vector changes <Florent Kermarrec>
* 4196708 - core/tlp: expose tags/tlp_req/tlp_cmp <Florent Kermarrec>
* 324ab72 - examples/targets: update crg with new phy (can't use pcie rst) <Florent Kermarrec>
* 14acea3 - software/linux/kernel/main: fix compilation on 4.11.0 and > kernels (thanks nanortemis) <Florent Kermarrec>
* b304a7a - software/linux/user: update dump_version <Florent Kermarrec>
* litescope changed from 1634fa3 to c1d8bdf
* c1d8bdf - core: fix Trigger flush when disabled <Florent Kermarrec>
* litevideo changed from 0993a4e to 98e145f
* 98e145f - Merge pull request #22 from rohitk-singh/regression-fix <enjoy-digital>
* 411669b - input/clocking/S7Clocking: fix clock-domains when split_clocking=False <Rohit Singh>
* 17ebc03 - output/hdmi: fix incorrect clock domain in S7HDMIOutEncoderSerializer <Rohit Singh>
* 1e51823 - driver/hdmi: fix sink connection <Rohit Singh>
* litex changed from v0.1-679-ga7378a72 to v0.1-710-gaf52842f
* af52842f - soc_sdram: add use_full_memory_we parameter to allow disabling vivado workaround on small l2 caches <Florent Kermarrec>
* 32543430 - build/lattice/common/LatticeECXTrellisImpl: add support for nbits == 1 <Florent Kermarrec>
* aabf042d - soc_sdram: don't generate sdram initialization error message when integrated_main_ram is used <Florent Kermarrec>
* f51ad436 - build/lattice/common: add LatticeiCE40DDROutput <Florent Kermarrec>
* 22ccf9dd - platforms/nexys_video: add LPC transceivers pins <Florent Kermarrec>
* 1d9c5588 - build/sim: add jtagremote module (thanks LamdaConcept) <Florent Kermarrec>
* 57b8bdd5 - soc/integration/soc_core: allow disabling wishbone timeout <Florent Kermarrec>
* 05dcb5ca - soc/interconnect/wishbone: increase bus error timeout to 1e6 cycles <Florent Kermarrec>
* 02708d3b - boards/platform/kc705: add sfp pins (both tx and rx) <Florent Kermarrec>
* 8344a6a4 - soc/cores/clock: add USIDELAYCTRL <Florent Kermarrec>
* 7e0dd376 - soc/integration/soc_sdram: round port.data_width/l2_size to nearest power of 2 when it's not the case <Florent Kermarrec>
* 871b958f - boards/targets: improve presentation <Florent Kermarrec>
* a318343a - boards/platforms/kcu105: add si570_refclk <Florent Kermarrec>
* 48312890 - boards/platforms/kc705: use vivado as default programmer <Florent Kermarrec>
* 1b23890e - soc/cores/clock: allow ClockSignal to be used for clkin <Florent Kermarrec>
* 387ee041 - build/sim/core: fix coverage <Florent Kermarrec>
* 482abf9b - build/sim/core: set -Wno-BLKANDNBLK (prevent blocking/non-blocking assigns on a same structure in system verilog) <Florent Kermarrec>
* 9c5f6547 - build/sim/core: set unroll-count to 256 to prevent Error-BLKLOOPINIT <Florent Kermarrec>
* f132012d - build/sim: disable Warning-WIDTH <Florent Kermarrec>
* 7c67bac7 - soc/cores/cpu/vexriscv: set default variant to None in add_sources <Florent Kermarrec>
* 648015d7 - soc/cores/cpu/vexriscv: move verilog variant selection to add_sources <Florent Kermarrec>
* 2b5a6f10 - targets/kcu105: use USMMCM <Florent Kermarrec>
* 86e19e62 - targets: pass speedgrade to S7PLL/S7MMCM <Florent Kermarrec>
* 2581a003 - soc/cores/clock: add Xilinx Ultrascale PLL/MMCM <Florent Kermarrec>
* 68e1dfca - boards: avoid duplicating platforms that can be found in migen/litex-buildenv <Florent Kermarrec>
* 041bf412 - soc/integration/cpu_interface: generate name for Memories in get_csr_header <Florent Kermarrec>
* 9f5d0cef - utils/litex_server: allow specify uart_baudrate as float <Florent Kermarrec>
* 2c43f6f7 - targets/ulx3s: use pll for phase shift, enable refresh, memtest ok <Florent Kermarrec>
* 5ef4d09c - targets/versa_ecp5: use pll for phase shift, enable refresh, memtest ok <Florent Kermarrec>
* 9c801fbe - soc/cores/clock/ECP5PLL: add basic phase support <Florent Kermarrec>
* a7b5b9d2 - litex_sim: simplify, change sdram module and enable sdram refresh. <Florent Kermarrec>
* migen changed from 0.6.dev-229-g5e7c71a to 0.6.dev-241-gafe4405
* afe4405 - sayma_rtm: add si5324_clkout_fabric and rtm_master_aux_clk <Sebastien Bourdeauducq>
* 3e6f39a - build/platforms: add upduino_v1 board initial support <msloniewski>
* 6902e6f - sayma_amc: remove outdated and inaccurate comment <Sebastien Bourdeauducq>
* 57c4467 - sayma_amc: add gth_clk200 pins <Sebastien Bourdeauducq>
* 81ba8ca - Updating Pins of de0nanosoc.py Platform file <AlexanderKnapik>
* 9da60e3 - sayma_rtm: offer 50T option <Sebastien Bourdeauducq>
* fd23e4f - sayma_rtm: fix si5324_clkin IOSTANDARD <Sebastien Bourdeauducq>
* ee0a827 - sayma_rtm: add DRTIO satellite signals <Sebastien Bourdeauducq>
* 8bfbdcb - sayma_rtm: cleanup resource numbers <Sebastien Bourdeauducq>
* 3d919dd - sayma_amc: add master SATA connector pins <Sebastien Bourdeauducq>
* 27e65bf - test: use environment variables to determine FPGA toolchain presence <William D. Jones>
* 5ab577e - Minor bugfix in docstring, missing comma at end of line. <Christian Vogel>
Full submodule status
--
6def7bc83dfb0338632e06a8b14c93faa6af8879 edid-decode (heads/master)
a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (heads/master)
d89b17177ae675a493ae100de66f64a759f4b82c litedram (remotes/origin/HEAD)
77fa4bfb1e452adb1fa34c1b0baede68c056763d liteeth (remotes/origin/HEAD)
3804c4947adedc6c720e3041e518627b0bf57f78 litepcie (remotes/origin/HEAD)
b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (heads/master)
c1d8bdf6f23b1070b8bd2dd277a4708863474148 litescope (remotes/origin/HEAD)
0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (heads/master)
98e145fba8c25394e9958bad67e2a457d145127e litevideo (remotes/origin/HEAD)
af52842fbb250d795d110d79fd2ac91442ad98b9 litex (v0.1-710-gaf52842f)
afe4405becdbc76539f0195c319367187012b05e migen (0.6.dev-241-gafe4405)
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@CarlFK just had this happen. It occasionally happens on Travis-CI too.
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