More than two cores

[pepijndevos]

I'm quite interested in making a SoC with more than two cores.

Looking at the code a bit it seems like maybe all that would be needed is to generalize the bus switch for more than two cores?

Maybe inter-core communication would require some thought as well.

[stnolting]

Hey @pepijndevos!

I'm quite interested in making a SoC with more than two cores.

The simplest approach would be to instantiate several NEORV32 tops, connect them to a global memory and daisy-chain the JTAG chain. This would then no longer be an SMP architecture, but rather a NUMA architecture.

Looking at the code a bit it seems like maybe all that would be needed is to generalize the bus switch for more than two cores?

Basically, you are right. The on-chip-debugger's debug module already supports up to 4 CPU cores (but that could be easily extended):

neorv32/rtl/core/neorv32_debug_dm.vhd

Lines 21 to 23 in 8ab1fec

	entity neorv32_debug_dm is
	generic (
	NUM_HARTS : natural range 1 to 4 := 1; -- number of physical CPU cores

The core-local interrupt supports even more CPU cores:

neorv32/rtl/core/neorv32_clint.vhd

Lines 21 to 23 in 8ab1fec

	entity neorv32_clint is
	generic (
	NUM_HARTS : natural range 1 to 4095 -- number of physical CPU cores

Maybe inter-core communication would require some thought as well.

Right. That would require a more complex fully-connected archiitecture since every core needs to be able to communicate with every other core.

---

When we introduced dual-core support, I did a few experiments with even more cores.

Two cores (without any CPU caches) surprisingly rarely get in each other's way (in terms of bus congestion). I think this is due to the fact that the CPU is a multi-cycle architecture that does not perform bus accesses in each and every cycle. With four cores, however, there was already a significant congestion in the central bus system.

With bigger/better CPU caches, however, you could certainly compensate for some of this.