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[sw/example] update RTE trap codes
1 parent a8cc817 commit f1d2ff0

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13 files changed

+87
-82
lines changed

13 files changed

+87
-82
lines changed

‎sw/example/bus_explorer/main.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -62,10 +62,10 @@ int main() {
6262

6363
// capture all exceptions and give debug info via UART
6464
neorv32_rte_setup();
65-
neorv32_rte_handler_install(RTE_TRAP_L_MISALIGNED, memory_trap_handler);
66-
neorv32_rte_handler_install(RTE_TRAP_L_ACCESS, memory_trap_handler);
67-
neorv32_rte_handler_install(RTE_TRAP_S_MISALIGNED, memory_trap_handler);
68-
neorv32_rte_handler_install(RTE_TRAP_S_ACCESS, memory_trap_handler);
65+
neorv32_rte_handler_install(TRAP_CODE_L_MISALIGNED, memory_trap_handler);
66+
neorv32_rte_handler_install(TRAP_CODE_L_ACCESS, memory_trap_handler);
67+
neorv32_rte_handler_install(TRAP_CODE_S_MISALIGNED, memory_trap_handler);
68+
neorv32_rte_handler_install(TRAP_CODE_S_ACCESS, memory_trap_handler);
6969

7070
// disable all interrupt sources
7171
neorv32_cpu_csr_write(CSR_MIE, 0);

‎sw/example/demo_clint/main.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -77,8 +77,8 @@ int main() {
7777
neorv32_clint_mtimecmp_set(-1);
7878

7979
// install CLINT handlers to RTE
80-
neorv32_rte_handler_install(RTE_TRAP_MTI, mti_irq_handler);
81-
neorv32_rte_handler_install(RTE_TRAP_MSI, msi_irq_handler);
80+
neorv32_rte_handler_install(TRAP_CODE_MTI, mti_irq_handler);
81+
neorv32_rte_handler_install(TRAP_CODE_MSI, msi_irq_handler);
8282

8383
// start real time clock
8484
neorv32_uart0_printf("\nStarting real-time clock demo...\n");

‎sw/example/demo_dma/main.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,7 @@ int main() {
6363
neorv32_uart0_printf("Descriptor FIFO depth: %u\n", neorv32_dma_get_descriptor_fifo_depth());
6464

6565
// install DMA interrupt handler
66-
neorv32_rte_handler_install(DMA_RTE_ID, dma_firq_handler);
66+
neorv32_rte_handler_install(DMA_TRAP_CODE, dma_firq_handler);
6767

6868
// enable DMA
6969
neorv32_dma_enable();

‎sw/example/demo_dual_core_rte/main.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -115,15 +115,15 @@ int app_main(void) {
115115

116116
// setup machine timer interrupt for ALL cores
117117
neorv32_clint_mtimecmp_set(0); // initialize core-specific MTIMECMP
118-
neorv32_rte_handler_install(RTE_TRAP_MTI, trap_handler_mtmi); // install trap handler
118+
neorv32_rte_handler_install(TRAP_CODE_MTI, trap_handler_mtmi); // install trap handler
119119
neorv32_cpu_csr_set(CSR_MIE, 1 << CSR_MIE_MTIE); // enable interrupt source
120120

121121
// setup machine software interrupt for ALL cores
122-
neorv32_rte_handler_install(RTE_TRAP_MSI, trap_handler_mswi); // install trap handler
122+
neorv32_rte_handler_install(TRAP_CODE_MSI, trap_handler_mswi); // install trap handler
123123
neorv32_cpu_csr_set(CSR_MIE, 1 << CSR_MIE_MSIE); // enable interrupt source
124124

125125
// setup machine environment call trap for ALL cores
126-
neorv32_rte_handler_install(RTE_TRAP_MENV_CALL, trap_handler_ecall); // install trap handler
126+
neorv32_rte_handler_install(TRAP_CODE_MENV_CALL, trap_handler_ecall); // install trap handler
127127

128128

129129
// trigger environment call exception (just to test the according handler)

‎sw/example/demo_emulate_unaligned/main.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// ================================================================================ //
22
// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //
33
// Copyright (c) NEORV32 contributors. //
4-
// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. //
4+
// Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved. //
55
// Licensed under the BSD-3-Clause license, see LICENSE for details. //
66
// SPDX-License-Identifier: BSD-3-Clause //
77
// ================================================================================ //
@@ -135,7 +135,7 @@ int main() {
135135
neorv32_uart0_printf("\nUnaligned load with emulation:\n");
136136

137137
// install trap handler for "unaligned load address" exception
138-
neorv32_rte_handler_install(RTE_TRAP_L_MISALIGNED, trap_handler_emulate_unaligned_lw);
138+
neorv32_rte_handler_install(TRAP_CODE_L_MISALIGNED, trap_handler_emulate_unaligned_lw);
139139

140140
addr = ((uint32_t)&data_block[0]) + 1; // = unaligned address
141141
neorv32_uart0_printf("MEM[0x%x] = ", addr);

‎sw/example/demo_gpio/main.c

Lines changed: 27 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -15,29 +15,34 @@
1515
/** User configuration */
1616
#define BAUD_RATE 19200
1717

18+
volatile uint32_t timestamp = 0;
19+
20+
21+
22+
static void puth(uint32_t num) {
23+
24+
int i = 0;
25+
const char hex_symbols[] = "0123456789ABCDEF";
26+
for (i=0; i<8; i++) {
27+
uint32_t index = (num >> (28 - 4*i)) & 0xF;
28+
neorv32_uart_tx_put(NEORV32_UART0, hex_symbols[index]);
29+
}
30+
neorv32_uart_tx_put(NEORV32_UART0, '\n');
31+
}
32+
33+
1834

1935
/**********************************************************************//**
2036
* GPIO input pin(s) interrupt handler.
2137
**************************************************************************/
2238
void gpio_interrupt_handler(void) {
2339

24-
// get bit mask of all those input pin that caused this interrupt
25-
uint32_t active = neorv32_gpio_irq_get();
26-
27-
// clear the active pins that we are "handling" here
28-
neorv32_gpio_irq_clr(active);
29-
30-
// "handle" the individual pin interrupts:
31-
// we just print the pin number of the triggering inputs
32-
int i;
33-
neorv32_uart0_printf("\nGPIO interrupt from pin(s): ");
34-
for (i=0; i<32; i++) {
35-
if (active & 1) {
36-
neorv32_uart0_printf("%u ", i);
37-
}
38-
active = active >> 1;
39-
}
40-
neorv32_uart0_printf("\n");
40+
neorv32_gpio_irq_clr(-1);
41+
uint32_t current = (uint32_t)neorv32_clint_time_get();
42+
uint32_t delta = current - timestamp;
43+
//neorv32_uart0_printf("0x%x 0x%x 0x%x\n", current, timestamp, delta);
44+
puth(delta);
45+
timestamp = current;
4146
}
4247

4348

@@ -68,17 +73,17 @@ int main(void) {
6873
}
6974

7075
// configure CPU's GPIO controller interrupt
71-
neorv32_rte_handler_install(GPIO_RTE_ID, gpio_interrupt_handler); // install GPIO trap handler
76+
neorv32_rte_handler_install(GPIO_TRAP_CODE, gpio_interrupt_handler); // install GPIO trap handler
7277
neorv32_cpu_csr_set(CSR_MIE, 1 << GPIO_FIRQ_ENABLE); // enable GPIO FIRQ channel
7378
neorv32_cpu_csr_set(CSR_MSTATUS, 1 << CSR_MSTATUS_MIE); // enable machine-mode interrupts
7479

7580
// configure GPIO input's IRQ trigger
7681
int i;
7782
for (i=0; i<32; i+=4) {
78-
neorv32_gpio_irq_setup(i+0, GPIO_TRIG_LEVEL_LOW); // this pin's interrupt fires on low-level
79-
neorv32_gpio_irq_setup(i+1, GPIO_TRIG_LEVEL_HIGH); // this pin's interrupt fires on high-level
80-
neorv32_gpio_irq_setup(i+2, GPIO_TRIG_EDGE_FALLING); // this pin's interrupt fires on a falling edge
81-
neorv32_gpio_irq_setup(i+3, GPIO_TRIG_EDGE_RISING); // this pin's interrupt fires on a rising edge
83+
neorv32_gpio_irq_setup(i+0, GPIO_TRIG_LEVEL_HIGH); // this pin's interrupt fires on low-level
84+
//neorv32_gpio_irq_setup(i+1, GPIO_TRIG_LEVEL_HIGH); // this pin's interrupt fires on high-level
85+
//neorv32_gpio_irq_setup(i+2, GPIO_TRIG_EDGE_FALLING); // this pin's interrupt fires on a falling edge
86+
//neorv32_gpio_irq_setup(i+3, GPIO_TRIG_EDGE_RISING); // this pin's interrupt fires on a rising edge
8287
}
8388

8489
// enable all GPIO input pin interrupts

‎sw/example/demo_gptmr/main.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,7 @@ int main() {
6060

6161

6262
// install GPTMR interrupt handler
63-
neorv32_rte_handler_install(GPTMR_RTE_ID, gptmr_firq_handler);
63+
neorv32_rte_handler_install(GPTMR_TRAP_CODE, gptmr_firq_handler);
6464

6565
// configure timer for 0.5Hz ticks with clock divisor = 8
6666
neorv32_gptmr_setup(CLK_PRSC_8, neorv32_sysinfo_get_clk() / (8 * 2));

‎sw/example/demo_semihosting/main.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,7 @@ int main() {
4545

4646
// hardware setup
4747
neorv32_rte_setup();
48-
neorv32_rte_handler_install(RTE_TRAP_BREAKPOINT, ebreak_trap_handler);
48+
neorv32_rte_handler_install(TRAP_CODE_BREAKPOINT, ebreak_trap_handler);
4949
neorv32_uart0_setup(BAUD_RATE, 0);
5050

5151
// say hello via UART0

‎sw/example/demo_slink/main.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -118,7 +118,7 @@ int main() {
118118
neorv32_slink_tx_clear();
119119

120120
// NEORV32 runtime environment: install SLINK FIRQ handler
121-
neorv32_rte_handler_install(SLINK_RTE_ID, slink_firq_handler);
121+
neorv32_rte_handler_install(SLINK_TRAP_CODE, slink_firq_handler);
122122
neorv32_cpu_csr_set(CSR_MIE, 1 << SLINK_FIRQ_ENABLE); // enable SLINK FIRQ
123123
neorv32_cpu_csr_set(CSR_MSTATUS, 1 << CSR_MSTATUS_MIE); // enable machine-mode interrupts
124124

‎sw/example/demo_spi_irq/main.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// ================================================================================ //
22
// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //
33
// Copyright (c) NEORV32 contributors. //
4-
// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. //
4+
// Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved. //
55
// Licensed under the BSD-3-Clause license, see LICENSE for details. //
66
// SPDX-License-Identifier: BSD-3-Clause //
77
// ================================================================================ //
@@ -78,7 +78,7 @@ int main()
7878
}
7979

8080
// enable IRQ system
81-
neorv32_rte_handler_install(SPI_RTE_ID, spi_irq_handler); // SPI to RTE
81+
neorv32_rte_handler_install(SPI_TRAP_CODE, spi_irq_handler); // SPI to RTE
8282
neorv32_cpu_csr_set(CSR_MIE, 1 << SPI_FIRQ_ENABLE); // enable SPI FIRQ
8383
neorv32_cpu_csr_set(CSR_MSTATUS, 1 << CSR_MSTATUS_MIE); // enable machine-mode interrupts
8484

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