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⚠️ [rte] rework RTE trap configuration
use the actual trap code from mcause instead of an explicit trap enumeration list
1 parent 2eae568 commit a8cc817

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2 files changed

+10
-55
lines changed

2 files changed

+10
-55
lines changed

‎sw/lib/include/neorv32.h

Lines changed: 10 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,14 @@ extern "C" {
2323
#include <inttypes.h>
2424
#include <stdlib.h>
2525

26+
// required for semihosting
27+
#if defined(STDIO_SEMIHOSTING)
28+
#include <stdio.h>
29+
#include <string.h>
30+
#include <fcntl.h> // for open
31+
#include <unistd.h> // for close
32+
#endif
33+
2634
/**********************************************************************//**
2735
* @name IO Address Space Map - Peripheral/IO Devices
2836
**************************************************************************/
@@ -71,98 +79,84 @@ extern "C" {
7179
/**@{*/
7280
#define TWD_FIRQ_ENABLE CSR_MIE_FIRQ0E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
7381
#define TWD_FIRQ_PENDING CSR_MIP_FIRQ0P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
74-
#define TWD_RTE_ID RTE_TRAP_FIRQ_0 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
7582
#define TWD_TRAP_CODE TRAP_CODE_FIRQ_0 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
7683
/**@}*/
7784
/** @name Custom Functions Subsystem (CFS) */
7885
/**@{*/
7986
#define CFS_FIRQ_ENABLE CSR_MIE_FIRQ1E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
8087
#define CFS_FIRQ_PENDING CSR_MIP_FIRQ1P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
81-
#define CFS_RTE_ID RTE_TRAP_FIRQ_1 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
8288
#define CFS_TRAP_CODE TRAP_CODE_FIRQ_1 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
8389
/**@}*/
8490
/** @name Primary Universal Asynchronous Receiver/Transmitter (UART0) */
8591
/**@{*/
8692
#define UART0_FIRQ_ENABLE CSR_MIE_FIRQ2E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
8793
#define UART0_FIRQ_PENDING CSR_MIP_FIRQ2P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
88-
#define UART0_RTE_ID RTE_TRAP_FIRQ_2 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
8994
#define UART0_TRAP_CODE TRAP_CODE_FIRQ_2 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
9095
/**@}*/
9196
/** @name Secondary Universal Asynchronous Receiver/Transmitter (UART1) */
9297
/**@{*/
9398
#define UART1_FIRQ_ENABLE CSR_MIE_FIRQ3E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
9499
#define UART1_FIRQ_PENDING CSR_MIP_FIRQ3P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
95-
#define UART1_RTE_ID RTE_TRAP_FIRQ_3 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
96100
#define UART1_TRAP_CODE TRAP_CODE_FIRQ_3 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
97101
/**@}*/
98102
/** @name Serial Peripheral Interface (SPI) */
99103
/**@{*/
100104
#define SPI_FIRQ_ENABLE CSR_MIE_FIRQ6E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
101105
#define SPI_FIRQ_PENDING CSR_MIP_FIRQ6P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
102-
#define SPI_RTE_ID RTE_TRAP_FIRQ_6 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
103106
#define SPI_TRAP_CODE TRAP_CODE_FIRQ_6 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
104107
/**@}*/
105108
/** @name Two-Wire Interface (TWI) */
106109
/**@{*/
107110
#define TWI_FIRQ_ENABLE CSR_MIE_FIRQ7E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
108111
#define TWI_FIRQ_PENDING CSR_MIP_FIRQ7P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
109-
#define TWI_RTE_ID RTE_TRAP_FIRQ_7 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
110112
#define TWI_TRAP_CODE TRAP_CODE_FIRQ_7 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
111113
/**@}*/
112114
/** @name General Purpose Input/Output Controller (GPIO) */
113115
/**@{*/
114116
#define GPIO_FIRQ_ENABLE CSR_MIE_FIRQ8E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
115117
#define GPIO_FIRQ_PENDING CSR_MIP_FIRQ8P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
116-
#define GPIO_RTE_ID RTE_TRAP_FIRQ_8 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
117118
#define GPIO_TRAP_CODE TRAP_CODE_FIRQ_8 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
118119
/**@}*/
119120
/** @name Smart LED Controller (NEOLED) */
120121
/**@{*/
121122
#define NEOLED_FIRQ_ENABLE CSR_MIE_FIRQ9E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
122123
#define NEOLED_FIRQ_PENDING CSR_MIP_FIRQ9P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
123-
#define NEOLED_RTE_ID RTE_TRAP_FIRQ_9 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
124124
#define NEOLED_TRAP_CODE TRAP_CODE_FIRQ_9 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
125125
/**@}*/
126126
/** @name Direct Memory Access Controller (DMA) */
127127
/**@{*/
128128
#define DMA_FIRQ_ENABLE CSR_MIE_FIRQ10E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
129129
#define DMA_FIRQ_PENDING CSR_MIP_FIRQ10P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
130-
#define DMA_RTE_ID RTE_TRAP_FIRQ_10 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
131130
#define DMA_TRAP_CODE TRAP_CODE_FIRQ_10 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
132131
/**@}*/
133132
/** @name Serial Data Interface (SDI) */
134133
/**@{*/
135134
#define SDI_FIRQ_ENABLE CSR_MIE_FIRQ11E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
136135
#define SDI_FIRQ_PENDING CSR_MIP_FIRQ11P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
137-
#define SDI_RTE_ID RTE_TRAP_FIRQ_11 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
138136
#define SDI_TRAP_CODE TRAP_CODE_FIRQ_11 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
139137
/**@}*/
140138
/** @name General Purpose Timer (GPTMR) */
141139
/**@{*/
142140
#define GPTMR_FIRQ_ENABLE CSR_MIE_FIRQ12E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
143141
#define GPTMR_FIRQ_PENDING CSR_MIP_FIRQ12P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
144-
#define GPTMR_RTE_ID RTE_TRAP_FIRQ_12 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
145142
#define GPTMR_TRAP_CODE TRAP_CODE_FIRQ_12 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
146143
/**@}*/
147144
/** @name 1-Wire Interface Controller (ONEWIRE) */
148145
/**@{*/
149146
#define ONEWIRE_FIRQ_ENABLE CSR_MIE_FIRQ13E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
150147
#define ONEWIRE_FIRQ_PENDING CSR_MIP_FIRQ13P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
151-
#define ONEWIRE_RTE_ID RTE_TRAP_FIRQ_13 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
152148
#define ONEWIRE_TRAP_CODE TRAP_CODE_FIRQ_13 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
153149
/**@}*/
154150
/** @name Stream Link Interface (SLINK) */
155151
/**@{*/
156152
#define SLINK_FIRQ_ENABLE CSR_MIE_FIRQ14E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
157153
#define SLINK_FIRQ_PENDING CSR_MIP_FIRQ14P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
158-
#define SLINK_RTE_ID RTE_TRAP_FIRQ_14 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
159154
#define SLINK_TRAP_CODE TRAP_CODE_FIRQ_14 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
160155
/**@}*/
161156
/** @name True-Random Number Generator (TRNG) */
162157
/**@{*/
163158
#define TRNG_FIRQ_ENABLE CSR_MIE_FIRQ15E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
164159
#define TRNG_FIRQ_PENDING CSR_MIP_FIRQ15P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
165-
#define TRNG_RTE_ID RTE_TRAP_FIRQ_15 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
166160
#define TRNG_TRAP_CODE TRAP_CODE_FIRQ_15 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
167161
/**@}*/
168162
/**@}*/
@@ -264,6 +258,8 @@ typedef union {
264258
#include "neorv32_uart.h"
265259
#include "neorv32_wdt.h"
266260

261+
// Legacy wrappers
262+
#include "neorv32_legacy.h"
267263

268264
#ifdef __cplusplus
269265
}

‎sw/lib/include/neorv32_rte.h

Lines changed: 0 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -16,47 +16,6 @@
1616

1717
#include <stdint.h>
1818

19-
/**********************************************************************//**
20-
* NEORV32 runtime environment trap IDs.
21-
**************************************************************************/
22-
/**@{*/
23-
24-
/**< Synchronous exceptions */
25-
#define RTE_TRAP_I_ACCESS TRAP_CODE_I_MISALIGNED /**< Instruction access fault */
26-
#define RTE_TRAP_I_ILLEGAL TRAP_CODE_I_ACCESS /**< Illegal instruction */
27-
#define RTE_TRAP_I_MISALIGNED TRAP_CODE_I_ILLEGAL /**< Instruction address misaligned */
28-
#define RTE_TRAP_BREAKPOINT TRAP_CODE_BREAKPOINT /**< Breakpoint (EBREAK instruction) */
29-
#define RTE_TRAP_L_MISALIGNED TRAP_CODE_L_MISALIGNED /**< Load address misaligned */
30-
#define RTE_TRAP_L_ACCESS TRAP_CODE_L_ACCESS /**< Load access fault */
31-
#define RTE_TRAP_S_MISALIGNED TRAP_CODE_S_MISALIGNED /**< Store address misaligned */
32-
#define RTE_TRAP_S_ACCESS TRAP_CODE_S_ACCESS /**< Store access fault */
33-
#define RTE_TRAP_UENV_CALL TRAP_CODE_UENV_CALL /**< Environment call from user mode (ECALL instruction) */
34-
#define RTE_TRAP_MENV_CALL TRAP_CODE_MENV_CALL /**< Environment call from machine mode (ECALL instruction) */
35-
#define RTE_TRAP_DOUBLE_TRAP TRAP_CODE_DOUBLE_TRAP /**< Double-trap */
36-
/**< Asynchronous exceptions */
37-
#define RTE_TRAP_MSI TRAP_CODE_MSI /**< Machine software interrupt */
38-
#define RTE_TRAP_MTI TRAP_CODE_MTI /**< Machine timer interrupt */
39-
#define RTE_TRAP_MEI TRAP_CODE_MEI /**< Machine external interrupt */
40-
#define RTE_TRAP_FIRQ_0 TRAP_CODE_FIRQ_0 /**< Fast interrupt channel 0 */
41-
#define RTE_TRAP_FIRQ_1 TRAP_CODE_FIRQ_1 /**< Fast interrupt channel 1 */
42-
#define RTE_TRAP_FIRQ_2 TRAP_CODE_FIRQ_2 /**< Fast interrupt channel 2 */
43-
#define RTE_TRAP_FIRQ_3 TRAP_CODE_FIRQ_3 /**< Fast interrupt channel 3 */
44-
#define RTE_TRAP_FIRQ_4 TRAP_CODE_FIRQ_4 /**< Fast interrupt channel 4 */
45-
#define RTE_TRAP_FIRQ_5 TRAP_CODE_FIRQ_5 /**< Fast interrupt channel 5 */
46-
#define RTE_TRAP_FIRQ_6 TRAP_CODE_FIRQ_6 /**< Fast interrupt channel 6 */
47-
#define RTE_TRAP_FIRQ_7 TRAP_CODE_FIRQ_7 /**< Fast interrupt channel 7 */
48-
#define RTE_TRAP_FIRQ_8 TRAP_CODE_FIRQ_8 /**< Fast interrupt channel 8 */
49-
#define RTE_TRAP_FIRQ_9 TRAP_CODE_FIRQ_9 /**< Fast interrupt channel 9 */
50-
#define RTE_TRAP_FIRQ_10 TRAP_CODE_FIRQ_10 /**< Fast interrupt channel 10 */
51-
#define RTE_TRAP_FIRQ_11 TRAP_CODE_FIRQ_11 /**< Fast interrupt channel 11 */
52-
#define RTE_TRAP_FIRQ_12 TRAP_CODE_FIRQ_12 /**< Fast interrupt channel 12 */
53-
#define RTE_TRAP_FIRQ_13 TRAP_CODE_FIRQ_13 /**< Fast interrupt channel 13 */
54-
#define RTE_TRAP_FIRQ_14 TRAP_CODE_FIRQ_14 /**< Fast interrupt channel 14 */
55-
#define RTE_TRAP_FIRQ_15 TRAP_CODE_FIRQ_15 /**< Fast interrupt channel 15 */
56-
/**< Total number of trap codes */
57-
#define NEORV32_RTE_NUM_TRAPS (2*32)
58-
/**@}*/
59-
6019
/**********************************************************************//**
6120
* @name Prototypes
6221
**************************************************************************/

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