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6fd7f88
Add CSR YAML file for Ssqosid:srmcfg
syedowaisalishah Apr 23, 2025
08084a3
Add Extension YAML file for Ssqosid
syedowaisalishah Apr 23, 2025
091c477
Merge branch 'main' into add-ssqosid-csr-yaml
syedowaisalishah Apr 27, 2025
ffcce03
Add Extension YAML file for Ssqosid
syedowaisalishah Apr 27, 2025
cdadf98
Add CSR YAML file for Ssqosid:srmcfg
syedowaisalishah Apr 27, 2025
bed59a8
Merge branch 'riscv-software-src:main' into add-ssqosid-csr-yaml
syedowaisalishah Apr 30, 2025
cefa26a
docs(csr): improve srmcfg register description and field details
syedowaisalishah Apr 30, 2025
10cc9f0
Merge branch 'main' into add-ssqosid-csr-yaml
syedowaisalishah May 2, 2025
2693eec
docs(csr): improve srmcfg register description
syedowaisalishah May 2, 2025
9af87be
Update .gitignore
syedowaisalishah May 2, 2025
b22aea6
Add CSR YAML file for Ssqosid:srmcfg
syedowaisalishah Apr 23, 2025
ee25208
Add Extension YAML file for Ssqosid
syedowaisalishah Apr 23, 2025
084c743
Add Extension YAML file for Ssqosid
syedowaisalishah Apr 27, 2025
8ff0e7e
Add CSR YAML file for Ssqosid:srmcfg
syedowaisalishah Apr 27, 2025
9e9d9f2
docs(csr): improve srmcfg register description and field details
syedowaisalishah Apr 30, 2025
04e166e
docs(csr): improve srmcfg register description
syedowaisalishah May 2, 2025
f47a908
Merge branch 'main' into add-ssqosid-csr-yaml
syedowaisalishah May 8, 2025
9185363
Merge branch 'riscv-software-src:main' into add-ssqosid-csr-yaml
syedowaisalishah May 9, 2025
9484dc9
Merge branch 'add-ssqosid-csr-yaml' of https://github.com/syedowaisal…
syedowaisalishah May 9, 2025
abcd342
feat(csr): add YAML file for Ssqosid:srmcfg
syedowaisalishah May 9, 2025
12a4d9b
feat(csr): add YAML file for Ssqosid:srmcfg
syedowaisalishah May 13, 2025
73e1a92
Merge branch 'main' into add-ssqosid-csr-yaml
syedowaisalishah May 15, 2025
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2 changes: 2 additions & 0 deletions .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -21,3 +21,5 @@ __pycache__/
.pytest_cache/
*.bak
*.log
__pycache__/
*.pyc
110 changes: 110 additions & 0 deletions arch/csr/Ssqosid/srmcfg.yaml
Original file line number Diff line number Diff line change
@@ -0,0 +1,110 @@
# yaml-language-server: $schema=../../../schemas/csr_schema.json
$schema: csr_schema.json#
kind: csr
name: srmcfg
long_name: Supervisor Resource Management Configuration
address: 0x181
priv_mode: S
length: SXLEN
definedBy: Ssqosid
description:
- id: csr-srmcfg-purpose
normative: true
text: |
The srmcfg register is used to configure a Resource Control ID (RCID) and a Monitoring Counter ID (MCID).
Both RCID and MCID are WARL fields.
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"WARL fields" means that, technically, an implementation can decide to accept any set of valid identifiers (including nothing) and reject the rest. We can't model that, so I suggest we don't try.

Practically, this usually means that an implementation is going to select some number of bits to implement (>= the size of the fields) for each. We can model that.

To reflect the number of implemented bits, we need a parameter in Ssqosid for each of RCID and MCID widths, and sw_write() functions to enforce it.

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@syedowaisalishah, have you had a chance to try this yet?

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@dhower-qc I haven’t had a chance to try this yet—I just finished the earlier part and will be starting on this next.

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ok, thanks for the update

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@dhower-qc, I’ve implemented the validation logic in the sw_write() function to enforce the WARL constraints for RCID and MCID. Since the YAML schema doesn't allow top-level parameters:, I hardcoded the masks directly in the IDL code like this:

value = csr_value;
rcid_mask = 0xFFF       # 12-bit RCID
mcid_mask = 0xFFF       # 12-bit MCID
rcid = csr_value & rcid_mask
mcid = (csr_value >> 16) & mcid_mask
value = (mcid << 16) | rcid

This effectively limits both fields to their respective implemented widths (12 bits here).
Is this the correct way to handle it, given the schema limitation?


- id: csr-srmcfg-field-usage
normative: true
text: |
The RCID and MCID accompany each request made by the hart to shared resource controllers.
The RCID is used to determine the resource allocations (e.g., cache occupancy limits, memory bandwidth limits, etc.) to enforce.
The MCID is used to identify a counter to monitor resource usage.

- id: csr-srmcfg-default-scope
normative: true
text: |
The RCID and MCID configured in the srmcfg CSR apply to all privilege modes of software execution on that hart by default,
but this behavior may be overridden by future extensions.

- id: csr-srmcfg-smstateen-interaction
normative: true
text: |
If extension Smstateen is implemented together with Ssqosid, then Ssqosid also requires the SRMCFG bit in mstateen0 to be implemented.
If mstateen0.SRMCFG is 0, attempts to access srmcfg in privilege modes less privileged than M-mode raise an illegal-instruction exception.
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I think this means you need to implement sw_read() and sw_write() to validate this restriction.


- id: csr-srmcfg-vsmode-exception
normative: true
text: |
If mstateen0.SRMCFG is 1 or if extension Smstateen is not implemented, attempts to access srmcfg when V=1 raise a virtual-instruction exception.
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This also needs to be similarly validated.

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@syedowaisalishah syedowaisalishah May 5, 2025

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@ThinkOpenly , I've implemented both sw_read() and sw_write() to enforce access restrictions based on Smstateen and the SRMCFG bit in mstateen0, as specified in the normative text. Here's what the logic looks like:

sw_read(): |
  if (has_ext("Smstateen")) {
    if (mode() < PrivilegeMode::M && !CSR[mstateen0].SRMCFG) {
      raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
    }
    if (virt() && CSR[mstateen0].SRMCFG) {
      raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
    }
  } else {
    if (virt()) {
      raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
    }
  }
  return self.value;

sw_write(csr_value): |
  if (has_ext("Smstateen")) {
    if (mode() < PrivilegeMode::M && !CSR[mstateen0].SRMCFG) {
      raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
    }
    if (virt() && CSR[mstateen0].SRMCFG) {
      raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
    }
  } else {
    if (virt()) {
      raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
    }
  }
  self.value = value;

However, I'm currently getting the following IDL validation error:
CSR 'mstateen0' is not defined
This is expected since mstateen0.yaml is introduced in PR #592, which hasn't been merged yet.
Could you please advise me on what I should do?

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I think #592 is getting close. I don't have much experience with this, but you can apparently rebase your branch on top of the branch for #592 and pick up those changes for your testing. Once #592 gets merged, your branch will automatically get rebased to main, and will continue working.

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@ThinkOpenly.
I struggled a bit with rebasing onto the branch from PR #592, so for testing purposes, I manually copied over the mstateen* CSR definitions and the Smstateen extension from that PR. I also added srmcfg as a field in mstateen0 to resolve the validation error.
With those changes, I was able to work through and resolve all the issues I faced during IDL writing—except for one that I’m still stuck on. Specifically, I get the following error:
A type error occurred no symbol named 'value' on line 146
idl code:

Here’s the relevant snippet:
return value;
I’m not sure what I’m doing wrong here. Do you have any guidance on how to resolve this?

sw_read(): |
  if (implemented?(ExtensionName::Smstateen)) {
    if (mode() < PrivilegeMode::M && CSR[mstateen0].SRMCFG == 0) {
      raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
    }
    if (virtual_mode?() && CSR[mstateen0].SRMCFG == 1) {
      raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
    }
  } else {
    if (virtual_mode?()) {
      raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
    }
  }
  return value;
  
  sw_write(csr_value): |
      if (implemented?(ExtensionName::Smstateen)) {
        if (mode() < PrivilegeMode::M && CSR[mstateen0].SRMCFG == 0) {
          raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
        }
        if (virtual_mode?() && CSR[mstateen0].SRMCFG == 1) {
          raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
        }
      } else {
        if (virtual_mode?()) {
          raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
        }
      }
      value = csr_value;

      rcid_mask = 0xFFF
      mcid_mask = 0xFFF

      rcid = csr_value & rcid_mask
      mcid = (csr_value >> 16) & mcid_mask

      value = (mcid << 16) | rcid


- id: csr-srmcfg-rcid-reset
normative: false
text: |
A reset value of 0 is suggested for the RCID field, matching resource controllers' default behavior of associating all capacity with RCID=0.

- id: csr-srmcfg-mcid-reset
normative: false
text: |
The MCID reset value does not affect functionality and may be implementation-defined.

- id: csr-srmcfg-id-bit-allocation
normative: false
text: |
Typically, fewer bits are allocated for RCID (e.g., to support tens of RCIDs) than for MCID (e.g., to support hundreds of MCIDs).

- id: csr-srmcfg-rcid-grouping
normative: false
text: |
A common RCID is usually used to group apps or VMs, pooling resource allocations to meet collective SLAs.

- id: csr-srmcfg-mcid-granularity
normative: false
text: |
If an SLA breach occurs, unique MCIDs enable granular monitoring, aiding decisions on resource adjustment,
associating a different RCID with a subset of members, or migrating members to other machines.
The larger pool of MCIDs speeds up this analysis.

- id: csr-srmcfg-privilege-behavior
normative: false
text: |
The RCID and MCID in srmcfg apply across all privilege levels on the hart.
Typically, higher-privilege modes don’t modify srmcfg, as they often serve lower-privileged tasks.
If differentiation is needed, higher privilege code can update srmcfg and restore it before returning to a lower privilege level.

- id: csr-srmcfg-vm-virtualization
normative: false
text: |
In VM environments, hypervisors usually manage resource allocations, keeping the Guest OS out of QoS flows.
If needed, the hypervisor can virtualize srmcfg CSR for a VM using the virtual-instruction exceptions triggered upon Guest access.

- id: csr-srmcfg-vs-mode-future
normative: false
text: |
If the direct selection of RCID and MCID by the VM becomes common and emulation overhead is an issue,
future extensions may allow VS-mode to use a selector for a hypervisor-configured set of CSRs holding RCID and MCID values designated for that Guest OS use.

- id: csr-srmcfg-context-switch
normative: false
text: |
During context switches, the supervisor may choose to execute with the srmcfg of the outgoing context to attribute the execution to it.
Prior to restoring the new context, it switches to the new VM’s srmcfg.
The supervisor can also use a separate configuration for execution not to be attributed to either context.

fields:
RCID:
location: 11-0
type: RW
long_name: Resource Control ID
description: |
The RCID is used to determine the resource allocations (e.g., cache occupancy limits,
memory bandwidth limits, etc.) to enforce.
reset_value: UNDEFINED_LEGAL
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I wonder if this should be 0, given the text:

A reset value of 0 is suggested for the RCID field

But, given the "suggested" language, I'm not sure, or if that implies a configuration parameter is required? @dhower-qc


MCID:
location: 27-16
type: RW
long_name: Monitoring Counter ID
description: |
The MCID is used to identify a counter to monitor resource usage.
reset_value: UNDEFINED_LEGAL
36 changes: 36 additions & 0 deletions arch/ext/Ssqosid.yaml
Original file line number Diff line number Diff line change
@@ -0,0 +1,36 @@
# yaml-language-server: $schema=../../schemas/ext_schema.json

$schema: "ext_schema.json#"
kind: extension
name: Ssqosid
type: privileged
long_name: Quality-of-Service Identifiers
description: |
Quality of Service (QoS) is defined as the minimal end-to-end performance guaranteed in advance by a service level agreement (SLA) to a workload.
Performance metrics might include measures such as instructions per cycle (IPC), latency of service, etc.

When multiple workloads execute concurrently on modern processors—equipped with large core counts, multiple cache hierarchies, and multiple memory
controllers—the performance of any given workload becomes less deterministic, or even non-deterministic, due to shared resource contention.

To manage performance variability, system software needs resource allocation and monitoring capabilities.
These capabilities allow for the reservation of resources like cache and bandwidth, thus meeting individual performance targets while minimizing interference.
For resource management, hardware should provide monitoring features that allow system software to profile workload resource consumption and allocate resources accordingly.

To facilitate this, the QoS Identifiers extension (Ssqosid) introduces the srmcfg register,
which configures a hart with two identifiers: a Resource Control ID (RCID) and a Monitoring Counter ID (MCID).
These identifiers accompany each request issued by the hart to shared resource controllers.

Additional metadata, like the nature of the memory access and the ID of the originating supervisor domain,
can accompany RCID and MCID. Resource controllers may use this metadata for differentiated service such as a different capacity allocation for code storage vs. data storage.
Resource controllers can use this data for security policies such as not exposing statistics of one security domain to another.

These identifiers are crucial for the RISC-V Capacity and Bandwidth Controller QoS Register Interface (CBQRI) specification,
which provides methods for setting resource usage limits and monitoring resource consumption.
The RCID controls resource allocations, while the MCID is used for tracking resource usage.

versions:
- version: "1.0.0"
state: ratified
ratification_date: "2024-06"
url: "https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-5308687-2025-04-22"
requires: { name: S, version: ~> 1.13 }
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