Add CSR YAML files for Sscofpmf: scountovf

arch/csr/Sscofpmf/scountovf.layout

@@ -0,0 +1,31 @@
+# scountovf.layout
+# Layout for scountovf CSR: each bit X reflects mhpmeventX.OF (for X = 3..31)
+bits[3]  = mhpmevent3.OF
+bits[4]  = mhpmevent4.OF
+bits[5]  = mhpmevent5.OF
+bits[6]  = mhpmevent6.OF
+bits[7]  = mhpmevent7.OF
+bits[8]  = mhpmevent8.OF
+bits[9]  = mhpmevent9.OF
+bits[10] = mhpmevent10.OF
+bits[11] = mhpmevent11.OF
+bits[12] = mhpmevent12.OF
+bits[13] = mhpmevent13.OF
+bits[14] = mhpmevent14.OF
+bits[15] = mhpmevent15.OF
+bits[16] = mhpmevent16.OF
+bits[17] = mhpmevent17.OF
+bits[18] = mhpmevent18.OF
+bits[19] = mhpmevent19.OF
+bits[20] = mhpmevent20.OF
+bits[21] = mhpmevent21.OF
+bits[22] = mhpmevent22.OF
+bits[23] = mhpmevent23.OF
+bits[24] = mhpmevent24.OF
+bits[25] = mhpmevent25.OF
+bits[26] = mhpmevent26.OF
+bits[27] = mhpmevent27.OF
+bits[28] = mhpmevent28.OF
+bits[29] = mhpmevent29.OF
+bits[30] = mhpmevent30.OF
+bits[31] = mhpmevent31.OF

arch/csr/Sscofpmf/scountovf.yaml

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+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: csr_schema.json#
+kind: csr
+name: scountovf
+long_name: Supervisor Count Overflow
+address: 0xDA0
+priv_mode: S
+length: 32
+definedBy: Sscofpmf
+description: |
+  A 32-bit read-only
+  register that contains shadow copies of the OF bits in the 29 `mhpmevent` CSRs
+  (`mhpmevent3` - `mhpmevent31`) — where `scountovf` bit X corresponds to `mhpmeventX`.
+
+  This register enables supervisor-level overflow interrupt handler
+  software to quickly and easily determine which counter(s) have overflowed
+  (without needing to make an execution environment call or series of calls ultimately up to M-mode)
+
+  Read access to bit X is subject to the same `mcounteren` (or `mcounteren` and `hcounteren`)
+  CSRs that mediate access to the `hpmcounter` CSRs by S-mode (or VS-mode).
+  In M-mode, `scountovf` bit X is always readable. In S/HS-mode, `scountovf` bit X is readable
+  when `mcounteren` bit X is set, and otherwise reads as zero. Similarly, in VS mode,
+  `scountovf` bit X is readable when `mcounteren` bit X and `hcounteren` bit X are both set, and otherwise reads as zero.
+
+fields:
+  OF3:
+    alias: mhpmevent3.OF
+    location: 3
+    type: RO
+    description: Shadow copy of mhpmevent3 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+
+  OF4:
+    alias: mhpmevent4.OF
+    location: 4
+    type: RO
+    description: Shadow copy of mhpmevent4 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+
+  OF5:
+    alias: mhpmevent5.OF
+    location: 5
+    type: RO
+    description: Shadow copy of mhpmevent5 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+
+  OF6:
+    alias: mhpmevent6.OF
+    location: 6
+    type: RO
+    description: Shadow copy of mhpmevent6 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+
+  OF7:
+    alias: mhpmevent7.OF
+    location: 7
+    type: RO
+    description: Shadow copy of mhpmevent7 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+
+  OF8:
+    alias: mhpmevent8.OF
+    location: 8
+    type: RO
+    description: Shadow copy of mhpmevent8 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+
+  OF9:
+    alias: mhpmevent9.OF
+    location: 9
+    type: RO
+    description: Shadow copy of mhpmevent9 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+
+  OF10:
+    alias: mhpmevent10.OF
+    location: 10
+    type: RO
+    description: Shadow copy of mhpmevent10 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+
+  OF11:
+    alias: mhpmevent11.OF
+    location: 11
+    type: RO
+    description: Shadow copy of mhpmevent11 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+
+  OF12:
+    alias: mhpmevent12.OF
+    location: 12
+    type: RO
+    description: Shadow copy of mhpmevent12 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+
+  OF13:
+    alias: mhpmevent13.OF
+    location: 13
+    type: RO
+    description: Shadow copy of mhpmevent13 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+
+  OF14:
+    alias: mhpmevent14.OF
+    location: 14
+    type: RO
+    description: Shadow copy of mhpmevent14 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+
+  OF15:
+    alias: mhpmevent15.OF
+    location: 15
+    type: RO
+    description: Shadow copy of mhpmevent15 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+
+  OF16:
+    alias: mhpmevent16.OF
+    location: 16
+    type: RO
+    description: Shadow copy of mhpmevent16 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+
+  OF17:
+    alias: mhpmevent17.OF
+    location: 17
+    type: RO
+    description: Shadow copy of mhpmevent17 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+
+  OF18:
+    alias: mhpmevent18.OF
+    location: 18
+    type: RO
+    description: Shadow copy of mhpmevent18 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+
+  OF19:
+    alias: mhpmevent19.OF
+    location: 19
+    type: RO
+    description: Shadow copy of mhpmevent19 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+
+  OF20:
+    alias: mhpmevent20.OF
+    location: 20
+    type: RO
+    description: Shadow copy of mhpmevent20 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+
+  OF21:
+    alias: mhpmevent21.OF
+    location: 21
+    type: RO
+    description: Shadow copy of mhpmevent21 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+
+  OF22:
+    alias: mhpmevent22.OF
+    location: 22
+    type: RO
+    description: Shadow copy of mhpmevent22 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+
+  OF23:
+    alias: mhpmevent23.OF
+    location: 23
+    type: RO
+    description: Shadow copy of mhpmevent23 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+
+  OF24:
+    alias: mhpmevent24.OF
+    location: 24
+    type: RO
+    description: Shadow copy of mhpmevent24 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+
+  OF25:
+    alias: mhpmevent25.OF
+    location: 25
+    type: RO
+    description: Shadow copy of mhpmevent25 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+
+  OF26:
+    alias: mhpmevent26.OF
+    location: 26
+    type: RO
+    description: Shadow copy of mhpmevent26 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+
+  OF27:
+    alias: mhpmevent27.OF
+    location: 27
+    type: RO
+    description: Shadow copy of mhpmevent27 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+
+  OF28:
+    alias: mhpmevent28.OF
+    location: 28
+    type: RO
+    description: Shadow copy of mhpmevent28 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+
+  OF29:
+    alias: mhpmevent29.OF
+    location: 29
+    type: RO
+    description: Shadow copy of mhpmevent29 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+
+  OF30:
+    alias: mhpmevent30.OF
+    location: 30
+    type: RO
+    description: Shadow copy of mhpmevent30 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+
+  OF31:
+    alias: mhpmevent31.OF
+    location: 31
+    type: RO
+    description: Shadow copy of mhpmevent31 overflow (OF) bit.
+    reset_value: UNDEFINED_LEGAL
+sw_read(): |
+  Bits<32> mask;
+  if (mode() == PrivilegeMode::VS) {
+    # in VS-mode, scountovf.OFX access is determined by mcounteren/hcounteren
+    mask = $bits(CSR[mcounteren]) & $bits(CSR[hcounteren]);
+  } else {
+    # in M-mode and S-mode, scountovf.OFX access is determined by mcounteren/scounteren
+    mask = $bits(CSR[mcounteren]) & $bits(CSR[scounteren]);
+  }
+
+  Bits<32> value =
+    (CSR[mhpmevent3].OF << 3) |
+    (CSR[mhpmevent4].OF << 4) |
+    (CSR[mhpmevent5].OF << 5) |
+    (CSR[mhpmevent6].OF << 6) |
+    (CSR[mhpmevent7].OF << 7) |
+    (CSR[mhpmevent8].OF << 8) |
+    (CSR[mhpmevent9].OF << 9) |
+    (CSR[mhpmevent10].OF << 10) |
+    (CSR[mhpmevent11].OF << 11) |
+    (CSR[mhpmevent12].OF << 12) |
+    (CSR[mhpmevent13].OF << 13) |
+    (CSR[mhpmevent14].OF << 14) |
+    (CSR[mhpmevent15].OF << 15) |
+    (CSR[mhpmevent16].OF << 16) |
+    (CSR[mhpmevent17].OF << 17) |
+    (CSR[mhpmevent18].OF << 18) |
+    (CSR[mhpmevent19].OF << 19) |
+    (CSR[mhpmevent20].OF << 20) |
+    (CSR[mhpmevent21].OF << 21) |
+    (CSR[mhpmevent22].OF << 22) |
+    (CSR[mhpmevent23].OF << 23) |
+    (CSR[mhpmevent24].OF << 24) |
+    (CSR[mhpmevent25].OF << 25) |
+    (CSR[mhpmevent26].OF << 26) |
+    (CSR[mhpmevent27].OF << 27) |
+    (CSR[mhpmevent28].OF << 28) |
+    (CSR[mhpmevent29].OF << 29) |
+    (CSR[mhpmevent30].OF << 30) |
+    (CSR[mhpmevent31].OF << 31);
+
+  return value & mask;