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@riscv-non-isa

RISC-V Non-ISA Specifications

The Open-Standard Instruction Set Architecture
README.md

Welcome to the RISC-V Non-ISA Specifications 👋

RISC-V Logo

Non-ISA specifications do not add new instructions, create or change opcodes, or in any way modify the RISC-V ISA. They do help us to develop an ecosystem around the ISA Specifications.

Things you'll find here include:

  • ABI Documentation
  • Architecture Tests
  • Specifications like Debug, Processor Trace, and Software Interrupts

If you don't find what you're looking for here, try one of our other GitHub organizations:

Popular repositories Loading

  1. riscv-asm-manual riscv-asm-manual Public

    RISC-V Assembly Programmer's Manual

    Makefile 1.5k 249

  2. riscv-elf-psabi-doc riscv-elf-psabi-doc Public

    A RISC-V ELF psABI Document

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  3. riscv-arch-test riscv-arch-test Public

    Assembly 564 230

  4. riscv-sbi-doc riscv-sbi-doc Public

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    Makefile 410 95

  5. rvv-intrinsic-doc rvv-intrinsic-doc Public

    C 335 98

  6. riscv-trace-spec riscv-trace-spec Public

    RISC-V Processor Trace Specification

    C 184 55

Repositories

Showing 10 of 34 repositories
  • rvv-intrinsic-doc Public
    riscv-non-isa/rvv-intrinsic-doc’s past year of commit activity
    C 335 BSD-3-Clause 98 22 9 Updated Jun 16, 2025
  • riscv-brs Public

    The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSVs) to interoperate with one another by providing expectations for the Operating System (OS) to utilize in acts of device discovery, system management, and other rich operations provided in this specification.

    riscv-non-isa/riscv-brs’s past year of commit activity
    TeX 49 CC-BY-4.0 20 15 0 Updated Jun 15, 2025
  • riscv-trace-spec Public

    RISC-V Processor Trace Specification

    riscv-non-isa/riscv-trace-spec’s past year of commit activity
    C 184 CC-BY-4.0 55 5 5 Updated Jun 13, 2025
  • iopmp-spec Public

    This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protection Unit of Input/Output devices, IOPMP for short, to regulate the accesses issued from the bus masters.

    riscv-non-isa/iopmp-spec’s past year of commit activity
    Makefile 29 CC-BY-4.0 8 1 2 Updated Jun 13, 2025
  • riscv-iommu Public

    RISC-V IOMMU Specification

    riscv-non-isa/riscv-iommu’s past year of commit activity
    C 119 CC-BY-4.0 23 0 5 Updated Jun 12, 2025
  • riscv-sbi-doc Public

    Documentation for the RISC-V Supervisor Binary Interface

    riscv-non-isa/riscv-sbi-doc’s past year of commit activity
    Makefile 410 CC-BY-4.0 95 11 0 Updated Jun 12, 2025
  • riscv-security-model Public

    RISC-V Security Model

    riscv-non-isa/riscv-security-model’s past year of commit activity
    Makefile 30 CC-BY-4.0 17 0 1 Updated Jun 11, 2025
  • riscv-elf-psabi-doc Public

    A RISC-V ELF psABI Document

    riscv-non-isa/riscv-elf-psabi-doc’s past year of commit activity
    Python 785 CC-BY-4.0 169 60 24 Updated Jun 11, 2025
  • riscv-c-api-doc Public

    Documentation of the RISC-V C API

    riscv-non-isa/riscv-c-api-doc’s past year of commit activity
    Makefile 76 CC-BY-4.0 45 17 5 Updated Jun 10, 2025
  • riscv-acpi-ffh Public

    The repo will be used to hold the draft non-ISA RISC-V ACPI Functional Fixed Hardware (FFH) specification

    riscv-non-isa/riscv-acpi-ffh’s past year of commit activity
    Makefile 4 CC-BY-4.0 4 1 2 Updated Jun 6, 2025
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