Advance Xqci version to 0.4, added instruction format information to …

cfgs/qc_iu/arch_overlay/ext/Xqci.yaml

@@ -57,6 +57,36 @@ Xqci:
     - [Xqcilo, "0.1.0"]
     - [Xqcilsm, "0.1.0"]
     - [Xqcisls, "0.1.0"]
+  - version: "0.4.0"
+    state: frozen
+    ratification_date: null
+    contributors:
+    - name: Albert Yosher
+      company: Qualcomm Technologies, Inc.
+      email: [email protected]
+    - name: Derek Hower
+      company: Qualcomm Technologies, Inc.
+      email: [email protected]
+    changes:
+      - Add information about instruction formats of each instruction
+      - Fix description and functionality of qc.c.extu instruction
+      - Fix description and functionality of qc.shladd instruction
+    implies:
+    - [Xqcia, "0.2.0"]
+    - [Xqciac, "0.2.0"]
+    - [Xqcibi, "0.2.0"]
+    - [Xqcibm, "0.2.0"]
+    - [Xqcicli, "0.2.0"]
+    - [Xqcicm, "0.2.0"]
+    - [Xqcics, "0.2.0"]
+    - [Xqcicsr, "0.2.0"]
+    - [Xqciint, "0.2.0"]
+    - [Xqcilb, "0.2.0"]
+    - [Xqcili, "0.2.0"]
+    - [Xqcilia, "0.2.0"]
+    - [Xqcilo, "0.2.0"]
+    - [Xqcilsm, "0.2.0"]
+    - [Xqcisls, "0.2.0"]
   description: |
     The Xqci extension includes a set of instructions that improve RISC-V code density and
     performance in microontrollers. It fills several gaps:
@@ -114,6 +144,238 @@ Xqci:
     follow the guidance for 48-bit instructions in the RISC-V standard, but are not allocated in reserved custom
     space since no such space has been defined by RISC-V International.
 
+    Extension-specific instruction formats ::
+    --
+    QC.EAI format used for 48-bit instructions that operate on 32-bit immediate argument.
+    --
+
+    [%autowidth, cols="4*", options="header"]
+    |===
+    ^|Field
+    ^|Start bit
+    ^|Width
+    ^|Description
+
+    |opcode
+    ^|0
+    ^|7
+    |Opcode field of 48-bit instructions is 0x1F
+
+    |rd
+    ^|7
+    ^|5
+    |Destination register
+
+    |func3
+    ^|12
+    ^|3
+    |Function field identifying instruction group
+
+    |f1
+    ^|15
+    ^|1
+    |Secondary function field
+
+    |imm[31:0]
+    ^|16
+    ^|32
+    |Immediate operand of 32 bits
+    |===
+
+    --
+    QC.EI format used for 48-bit instructions that operate on 26-bit immediate argument, including loads.
+    --
+
+    [%autowidth, cols="4*", options="header"]
+    |===
+    ^|Field
+    ^|Start bit
+    ^|Width
+    ^|Description
+
+    |opcode
+    ^|0
+    ^|7
+    |Opcode field of 48-bit instructions is 0x1F
+
+    |rd
+    ^|7
+    ^|5
+    |Destination register
+
+    |func3
+    ^|12
+    ^|3
+    |Function field identifying instruction group
+
+    |rs1
+    ^|15
+    ^|5
+    |Register argument
+
+    |imm[9:0]
+    ^|20
+    ^|10
+    |Immediate operand of 26 bits, the 10 LSBs
+
+    |func2
+    ^|30
+    ^|2
+    |Secondary function field
+
+    |imm[25:10]
+    ^|32
+    ^|16
+    |Immediate operand of 26 bits, the 16 MSBs
+    |===
+
+    --
+    QC.EB format used for 48-bit branch instructions that compare register with 16-bit immediate.
+    --
+
+    [%autowidth, cols="4*", options="header"]
+    |===
+    ^|Field
+    ^|Start bit
+    ^|Width
+    ^|Description
+
+    |opcode
+    ^|0
+    ^|7
+    |Opcode field of 48-bit instructions is 0x1F
+
+    |imm[4:1,11]
+    ^|7
+    ^|5
+    |Bits of immediate value of branch target
+
+    |func3
+    ^|12
+    ^|3
+    |Function field identifying instruction group
+
+    |rs1
+    ^|15
+    ^|5
+    |Register argument
+
+    |func5
+    ^|20
+    ^|5
+    |Secondary function field
+
+    |imm[12,10:5]
+    ^|25
+    ^|7
+    |Bits of immediate value of branch target
+
+    |simm[15:0]
+    ^|32
+    ^|16
+    |Immediate operand of 16 bits to compare with register
+    |===
+
+    --
+    QC.EJ format used for 48-bit jump/call instructions with 32-bit immediate target address.
+    --
+
+    [%autowidth, cols="4*", options="header"]
+    |===
+    ^|Field
+    ^|Start bit
+    ^|Width
+    ^|Description
+
+    |opcode
+    ^|0
+    ^|7
+    |Opcode field of 48-bit instructions is 0x1F
+
+    |imm[4:1,11]
+    ^|7
+    ^|5
+    |Bits of immediate value of branch target
+
+    |func3
+    ^|12
+    ^|3
+    |Function field identifying instruction group
+
+    |func2
+    ^|15
+    ^|2
+    |Secondary function field
+
+    |imm[15:13]
+    ^|17
+    ^|3
+    |Bits of immediate value of branch target
+
+    |func5
+    ^|20
+    ^|5
+    |Secondary function field
+
+    |imm[12,10:5]
+    ^|25
+    ^|7
+    |Bits of immediate value of branch target
+
+    |imm[31:16]
+    ^|32
+    ^|16
+    |The 16 MSBs of immediate value of branch target
+    |===
+
+    --
+    QC.ES format used for 48-bit store instructions with 26-bit immediate offset.
+    --
+
+    [%autowidth.stretch]
+    |===
+    |Field|Start bit|Width|Description
+
+    |opcode
+    ^|0
+    ^|7
+    |Opcode field of 48-bit instructions is 0x1F
+
+    |imm[4:0]
+    ^|7
+    ^|5
+    |Immediate operand of 26 bits offset, the 5 LSBs
+
+    |func3
+    ^|12
+    ^|3
+    |Function field identifying instruction group
+
+    |rs1
+    ^|15
+    ^|5
+    |Register argument used as base address
+
+    |rs2
+    ^|20
+    ^|5
+    |Register argument to be saved
+
+    |imm[9:5]
+    ^|25
+    ^|5
+    |Immediate operand of 26 bits offset, the 5 bits
+
+    |func2
+    ^|30
+    ^|2
+    |Secondary function field
+
+    |imm[25:10]
+    ^|32
+    ^|16
+    |Immediate operand of 26 bits offset, the 16 MSBs
+    |===
   doc_license:
     name: Creative Commons Attribution 4.0 International License
     url: https://creativecommons.org/licenses/by/4.0/

cfgs/qc_iu/arch_overlay/ext/Xqcia.yaml

@@ -14,6 +14,18 @@ Xqcia:
     - name: Derek Hower
       company: Qualcomm Technologies, Inc.
       email: [email protected]
+  - version: "0.2.0"
+    state: frozen
+    ratification_date: null
+    contributors:
+    - name: Albert Yosher
+      company: Qualcomm Technologies, Inc.
+      email: [email protected]
+    - name: Derek Hower
+      company: Qualcomm Technologies, Inc.
+      email: [email protected]
+    changes:
+      - Add information about instruction formats of each instruction
   description: |
     The Xqcia extension includes eleven instructions to perform integer arithmetic.
 

cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml

@@ -14,6 +14,19 @@ Xqciac:
     - name: Derek Hower
       company: Qualcomm Technologies, Inc.
       email: [email protected]
+  - version: "0.2.0"
+    state: frozen
+    ratification_date: null
+    contributors:
+    - name: Albert Yosher
+      company: Qualcomm Technologies, Inc.
+      email: [email protected]
+    - name: Derek Hower
+      company: Qualcomm Technologies, Inc.
+      email: [email protected]
+    changes:
+      - Add information about instruction formats of each instruction
+      - Fix description and functionality of qc.shladd instruction
   description: |
     The Xqciac extension includes three instructions to accelerate common
     address calculations.

cfgs/qc_iu/arch_overlay/ext/Xqcibi.yaml

@@ -14,6 +14,18 @@ Xqcibi:
     - name: Derek Hower
       company: Qualcomm Technologies, Inc.
       email: [email protected]
+  - version: "0.2.0"
+    state: frozen
+    ratification_date: null
+    contributors:
+    - name: Albert Yosher
+      company: Qualcomm Technologies, Inc.
+      email: [email protected]
+    - name: Derek Hower
+      company: Qualcomm Technologies, Inc.
+      email: [email protected]
+    changes:
+      - Add information about instruction formats of each instruction
   description: |
     The Xqcibi extension includes twelve conditional branch instructions that use an immediate
     operand for a source.

cfgs/qc_iu/arch_overlay/ext/Xqcibm.yaml

@@ -14,6 +14,19 @@ Xqcibm:
     - name: Derek Hower
       company: Qualcomm Technologies, Inc.
       email: [email protected]
+  - version: "0.2.0"
+    state: frozen
+    ratification_date: null
+    contributors:
+    - name: Albert Yosher
+      company: Qualcomm Technologies, Inc.
+      email: [email protected]
+    - name: Derek Hower
+      company: Qualcomm Technologies, Inc.
+      email: [email protected]
+    changes:
+      - Add information about instruction formats of each instruction
+      - Fix description and functionality of qc.c.extu instruction
   description: |
     The Xqcibm extension includes thirty eight instructions that perform bit manipulation,
     include insertion and extraction.

cfgs/qc_iu/arch_overlay/ext/Xqcicli.yaml

@@ -14,6 +14,18 @@ Xqcicli:
     - name: Derek Hower
       company: Qualcomm Technologies, Inc.
       email: [email protected]
+  - version: "0.2.0"
+    state: frozen
+    ratification_date: null
+    contributors:
+    - name: Albert Yosher
+      company: Qualcomm Technologies, Inc.
+      email: [email protected]
+    - name: Derek Hower
+      company: Qualcomm Technologies, Inc.
+      email: [email protected]
+    changes:
+      - Add information about instruction formats of each instruction
   description: |
     The Xqcicli extension includes twelve instructions that conditionally
     load an immediate value.

cfgs/qc_iu/arch_overlay/ext/Xqcicm.yaml

@@ -14,6 +14,18 @@ Xqcicm:
     - name: Derek Hower
       company: Qualcomm Technologies, Inc.
       email: [email protected]
+  - version: "0.2.0"
+    state: frozen
+    ratification_date: null
+    contributors:
+    - name: Albert Yosher
+      company: Qualcomm Technologies, Inc.
+      email: [email protected]
+    - name: Derek Hower
+      company: Qualcomm Technologies, Inc.
+      email: [email protected]
+    changes:
+      - Add information about instruction formats of each instruction
   description: |
     The Xqcicm extension includes thirteen conditional move instructions.