RTL optimizations for Verilator #66
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Verilator does not include a special case for (2 ** X), making this very slow. This change increases simulation speed with Verilator by around 2 percent for the entire Cheshire SoC.
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This patch replaces some
2 ** Xconstructs by the equivalent1 << X. This is significantly faster when using Verilator, which lacks a special case optimization for powers of two and falls back to an iterative approach.This change increases simulation performance using Verilator on the Cheshire SoC (pulp-platform/cheshire#230) by roughly 2 percent.
I have also added an
ifndefso the instruction tracer can be disabled by definingCVA6_NO_TRACE.Note: This PR targets the
pulp-v1branch that is currently used by Cheshire.