Introduce width parameter

Expose the width (or W internally) parameter to set the SERV
datapath width.

Note: Only width=1 is function at this time.

Author: olofk

bench/servant_sim.v

@@ -8,6 +8,7 @@ module servant_sim
 
    parameter memfile = "";
    parameter memsize = 8192;
+   parameter width = 1;
    parameter with_csr = 1;
    parameter compressed = 0;
    parameter align = compressed;
@@ -22,6 +23,7 @@ module servant_sim
    servant
      #(.memfile  (memfile),
        .memsize  (memsize),
+       .width    (width),
        .sim      (1),
        .with_csr (with_csr),
        .compress (compressed[0:0]),

rtl/serv_rf_top.v

@@ -28,7 +28,8 @@ module serv_rf_top
      */
     parameter RESET_STRATEGY = "MINI",
     parameter WITH_CSR = 1,
-    parameter RF_WIDTH = 2,
+    parameter W        = 1,
+    parameter RF_WIDTH = W * 2,
 	parameter RF_L2D   = $clog2((32+(WITH_CSR*4))*32/RF_WIDTH))
   (
    input wire 	      clk,
@@ -86,13 +87,13 @@ module serv_rf_top
    wire [4+WITH_CSR:0] wreg1;
    wire 	      wen0;
    wire 	      wen1;
-   wire 	      wdata0;
-   wire 	      wdata1;
+   wire [W-1:0]	      wdata0;
+   wire [W-1:0]	      wdata1;
    wire [4+WITH_CSR:0] rreg0;
    wire [4+WITH_CSR:0] rreg1;
    wire 	      rf_ready;
-   wire 	      rdata0;
-   wire 	      rdata1;
+   wire [W-1:0]	      rdata0;
+   wire [W-1:0]	      rdata1;
 
    wire [RF_L2D-1:0]   waddr;
    wire [RF_WIDTH-1:0] wdata;
@@ -104,7 +105,8 @@ module serv_rf_top
    serv_rf_ram_if
      #(.width    (RF_WIDTH),
        .reset_strategy (RESET_STRATEGY),
-       .csr_regs (CSR_REGS))
+       .csr_regs (CSR_REGS),
+       .W(W))
    rf_ram_if
      (.i_clk    (clk),
       .i_rst    (i_rst),
@@ -147,7 +149,8 @@ module serv_rf_top
        .WITH_CSR (WITH_CSR),
        .MDU(MDU),
        .COMPRESSED(COMPRESSED),
-       .ALIGN(ALIGN))
+       .ALIGN(ALIGN),
+       .W(W))
    cpu
      (
       .clk      (clk),

rtl/serv_top.v

@@ -2,6 +2,8 @@
 
 module serv_top
   #(parameter WITH_CSR = 1,
+    parameter	    W = 1,
+    parameter	    B = W-1,
     parameter PRE_REGISTER = 1,
     parameter RESET_STRATEGY = "MINI",
     parameter RESET_PC = 32'd0,
@@ -43,12 +45,12 @@ module serv_top
    output wire [4+WITH_CSR:0] o_wreg1,
    output wire 		      o_wen0,
    output wire 		      o_wen1,
-   output wire 		      o_wdata0,
-   output wire 		      o_wdata1,
+   output wire [B:0] o_wdata0,
+   output wire [B:0] o_wdata1,
    output wire [4+WITH_CSR:0] o_rreg0,
    output wire [4+WITH_CSR:0] o_rreg1,
-   input wire 		      i_rdata0,
-   input wire 		      i_rdata1,
+   input wire  [B:0] i_rdata0,
+   input wire  [B:0] i_rdata1,
 
    output wire [31:0] 	      o_ibus_adr,
    output wire 		      o_ibus_cyc,
@@ -92,18 +94,18 @@ module serv_top
    wire 	 rd_alu_en;
    wire 	 rd_csr_en;
    wire 	 rd_mem_en;
-   wire          ctrl_rd;
-   wire          alu_rd;
-   wire          mem_rd;
-   wire          csr_rd;
+   wire [B:0]    ctrl_rd;
+   wire [B:0]    alu_rd;
+   wire [B:0]    mem_rd;
+   wire [B:0]    csr_rd;
    wire 	 mtval_pc;
 
    wire          ctrl_pc_en;
    wire          jump;
    wire          jal_or_jalr;
    wire          utype;
    wire 	 mret;
-   wire          imm;
+   wire [B:0]    imm;
    wire 	 trap;
    wire 	 pc_rel;
    wire          iscomp;
@@ -127,8 +129,8 @@ module serv_top
    wire 	 bufreg_rs1_en;
    wire 	 bufreg_imm_en;
    wire 	 bufreg_clr_lsb;
-   wire 	 bufreg_q;
-   wire 	 bufreg2_q;
+   wire [B:0]    bufreg_q;
+   wire [B:0]    bufreg2_q;
    wire [31:0] dbus_rdt;
    wire        dbus_ack;
 
@@ -139,11 +141,11 @@ module serv_top
    wire          alu_cmp;
    wire [2:0]    alu_rd_sel;
 
-   wire          rs1;
-   wire          rs2;
+   wire [B:0]    rs1;
+   wire [B:0]    rs2;
    wire          rd_en;
 
-   wire          op_b;
+   wire [B:0]    op_b;
    wire          op_b_sel;
 
    wire          mem_signed;
@@ -156,20 +158,20 @@ module serv_top
 
    wire 	 mem_misalign;
 
-   wire 	 bad_pc;
+   wire [B:0]    bad_pc;
 
    wire 	 csr_mstatus_en;
    wire 	 csr_mie_en;
    wire 	 csr_mcause_en;
    wire [1:0]	 csr_source;
-   wire 	 csr_imm;
+   wire	[B:0]	 csr_imm;
    wire 	 csr_d_sel;
    wire 	 csr_en;
    wire [1:0] 	 csr_addr;
-   wire 	 csr_pc;
+   wire [B:0]    csr_pc;
    wire 	 csr_imm_en;
-   wire 	 csr_in;
-   wire 	 rf_csr_out;
+   wire [B:0]    csr_in;
+   wire [B:0]    rf_csr_out;
    wire 	 dbus_en;
 
    wire 	 new_irq;
@@ -226,7 +228,8 @@ module serv_top
      #(.RESET_STRATEGY (RESET_STRATEGY),
        .WITH_CSR (WITH_CSR[0:0]),
        .MDU(MDU),
-       .ALIGN(ALIGN))
+       .ALIGN(ALIGN),
+       .W(W))
    state
      (
       .i_clk (clk),
@@ -420,7 +423,8 @@ module serv_top
    serv_ctrl
      #(.RESET_PC (RESET_PC),
        .RESET_STRATEGY (RESET_STRATEGY),
-       .WITH_CSR (WITH_CSR))
+       .WITH_CSR (WITH_CSR),
+       .W (W))
    ctrl
      (
       .clk        (clk),
@@ -447,7 +451,7 @@ module serv_top
       //External
       .o_ibus_adr (wb_ibus_adr));
 
-   serv_alu alu
+   serv_alu #(.W (W)) alu
      (
       .clk        (clk),
       //State
@@ -467,7 +471,7 @@ module serv_top
       .o_rd       (alu_rd));
 
    serv_rf_if
-     #(.WITH_CSR (WITH_CSR))
+     #(.WITH_CSR (WITH_CSR), .W(W))
    rf_if
      (//RF interface
       .i_cnt_en    (cnt_en),
@@ -485,7 +489,7 @@ module serv_top
       //Trap interface
       .i_trap      (trap),
       .i_mret      (mret),
-      .i_mepc      (wb_ibus_adr[0]),
+      .i_mepc      (wb_ibus_adr[B:0]),
       .i_mtval_pc  (mtval_pc),
       .i_bufreg_q  (bufreg_q),
       .i_bad_pc    (bad_pc),
@@ -516,7 +520,8 @@ module serv_top
       .o_csr       (rf_csr_out));
 
    serv_mem_if
-     #(.WITH_CSR (WITH_CSR[0:0]))
+     #(.WITH_CSR (WITH_CSR[0:0]),
+       .W (W))
    mem_if
      (
       .i_clk        (clk),
@@ -539,7 +544,8 @@ module serv_top
    generate
       if (|WITH_CSR) begin : gen_csr
 	 serv_csr
-	   #(.RESET_STRATEGY (RESET_STRATEGY))
+	   #(.RESET_STRATEGY (RESET_STRATEGY),
+	     .W(W))
 	 csr
 	   (
 	    .i_clk        (clk),
@@ -574,8 +580,8 @@ module serv_top
 	    .i_rs1        (rs1),
 	    .o_q          (csr_rd));
       end else begin : gen_no_csr
-	 assign csr_in = 1'b0;
-	 assign csr_rd = 1'b0;
+	 assign csr_in = {W{1'b0}};
+	 assign csr_rd = {W{1'b0}};
 	 assign new_irq = 1'b0;
       end
    endgenerate
@@ -597,7 +603,7 @@ module serv_top
 
       /* Store data written to rd */
       if (o_wen0)
-        rvfi_rd_wdata <= {o_wdata0,rvfi_rd_wdata[31:1]};
+        rvfi_rd_wdata <= {o_wdata0,rvfi_rd_wdata[31:W]};
 
       if (cnt_done & ctrl_pc_en) begin
          rvfi_pc_rdata <= pc;
@@ -626,8 +632,8 @@ module serv_top
 	 rvfi_rd_addr  <= rd_addr;
       end
       if (rs_en) begin
-         rvfi_rs1_rdata <= {!immdec_en[1] & rs1,rvfi_rs1_rdata[31:1]};
-         rvfi_rs2_rdata <= {!immdec_en[2] & rs2,rvfi_rs2_rdata[31:1]};
+         rvfi_rs1_rdata <= {(!immdec_en[1] ? rs1 : {W{1'b0}}),rvfi_rs1_rdata[31:W]};
+         rvfi_rs2_rdata <= {(!immdec_en[2] ? rs2 : {W{1'b0}}),rvfi_rs2_rdata[31:W]};
       end
 
       if (i_dbus_ack) begin

servant.core

@@ -649,6 +649,7 @@ targets:
       - uart_baudrate
       - vcd
       - vcd_start
+      - width
       - compressed
       - align
       - with_csr=1
@@ -744,6 +745,11 @@ parameters:
     description : Delay start of VCD dumping until the specified time
     paramtype   : plusarg
 
+  width:
+    datatype    : int
+    description : Interal datapath width (1=SERV, 4=QERV)
+    paramtype   : vlogparam
+
   with_csr:
     datatype    : int
     description : Enable/Disable CSR support

servant/servant.v

@@ -8,6 +8,7 @@ module servant
    parameter memfile = "zephyr_hello.hex";
    parameter memsize = 8192;
    parameter reset_strategy = "MINI";
+   parameter width = 1;
    parameter sim = 0;
    parameter with_csr = 1;
    parameter [0:0] compress = 0;
@@ -23,7 +24,7 @@ module servant
    localparam	   aw = $clog2(memsize);
    localparam	   csr_regs = with_csr*4;
 
-   localparam	   rf_width = 2;
+   localparam	   rf_width = width * 2;
    localparam	   rf_l2d   = $clog2((32+csr_regs)*32/rf_width);
 
    wire 	timer_irq;
@@ -133,7 +134,7 @@ module servant
       .o_rdata  (rf_rdata));
 
    servile
-     #(.rf_width (rf_width),
+     #(.width    (width),
        .sim      (sim[0]),
        .with_c   (compress[0]),
        .with_csr (with_csr[0]),
@@ -159,7 +160,7 @@ module servant
       .o_wb_ext_stb   (wb_ext_stb),
       .i_wb_ext_rdt   (wb_ext_rdt),
       .i_wb_ext_ack   (wb_ext_ack),
-      
+
       .o_rf_waddr  (rf_waddr),
       .o_rf_wdata  (rf_wdata),
       .o_rf_wen    (rf_wen),

servile/servile.v

@@ -8,14 +8,16 @@
 `default_nettype none
 module servile
   #(
+    parameter       width = 1,
     parameter	    reset_pc = 32'h00000000,
     parameter	    reset_strategy = "MINI",
-    parameter	    rf_width = 8,
+    parameter	    rf_width = 2*width,
     parameter [0:0] sim = 1'b0,
     parameter [0:0] with_c = 1'b0,
     parameter [0:0] with_csr = 1'b0,
     parameter [0:0] with_mdu = 1'b0,
     //Internally calculated. Do not touch
+    parameter	    B = width-1,
     parameter	    regs = 32+with_csr*4,
     parameter	    rf_l2d = $clog2(regs*32/rf_width))
   (
@@ -78,13 +80,13 @@ module servile
    wire [$clog2(regs)-1:0] wreg1;
    wire 		   wen0;
    wire 		   wen1;
-   wire 		   wdata0;
-   wire 		   wdata1;
+   wire [B:0]		   wdata0;
+   wire [B:0]		   wdata1;
    wire [$clog2(regs)-1:0] rreg0;
    wire [$clog2(regs)-1:0] rreg1;
    wire 		   rf_ready;
-   wire 		   rdata0;
-   wire 		   rdata1;
+   wire [B:0]		   rdata0;
+   wire [B:0]		   rdata1;
 
    wire [31:0]		   mdu_rs1;
    wire [31:0]		   mdu_rs2;
@@ -149,6 +151,7 @@ module servile
 
    serv_rf_ram_if
      #(.width    (rf_width),
+       .W        (width),
        .reset_strategy (reset_strategy),
        .csr_regs (with_csr*4))
    rf_ram_if
@@ -196,6 +199,7 @@ module servile
    serv_top
      #(
        .WITH_CSR       (with_csr?1:0),
+       .W              (width),
        .PRE_REGISTER   (1'b1),
        .RESET_STRATEGY (reset_strategy),
        .RESET_PC       (reset_pc),