Skip to content

Commit 1c5d44e

Browse files
committed
Make CSR module 4-bit compatible
1 parent 4f04e9d commit 1c5d44e

File tree

1 file changed

+11
-1
lines changed

1 file changed

+11
-1
lines changed

rtl/serv_csr.v

+11-1
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,17 @@ module serv_csr
6565
(i_csr_source == CSR_SOURCE_CSR) ? csr_out :
6666
{W{1'bx}};
6767

68-
assign csr_out = (i_mstatus_en & i_en & ((mstatus_mie & i_cnt3) | (i_cnt11 | i_cnt12))) |
68+
wire [B:0] mstatus;
69+
70+
generate
71+
if (W==1) begin : gen_mstatus_w1
72+
assign mstatus = ((mstatus_mie & i_cnt3) | (i_cnt11 | i_cnt12));
73+
end else if (W==4) begin : gen_mstatus_w4
74+
assign mstatus = {i_cnt11 | (mstatus_mie & i_cnt3), 2'b00, i_cnt12};
75+
end
76+
endgenerate
77+
78+
assign csr_out = ({W{i_mstatus_en & i_en}} & mstatus) |
6979
i_rf_csr_out |
7080
({W{i_mcause_en & i_en}} & mcause);
7181

0 commit comments

Comments
 (0)