Subtile syntax

[tangxifan]

Motivate of the pull request

• To address an existing issue. If so, please provide a link to the issue: Splitting pin locations for a tile with capacity >1 #774
• Breaking new feature. If so, please describe details in the description part.

Describe the technical details

What is currently done? (Provide issue link if applicable)

What does this pull request change?

This PR improves in the following aspects:

• Now VPR's arch parser supports more flexible pin location assignment string, when capacity > 1
• Added a dedicated test case to validate the correctness
• Update documentation about the new XML syntax

Which part of the code base require a change

• VPR
• Tileable routing architecture generator
• OpenFPGA libraries
• FPGA-Verilog
• FPGA-Bitstream
• FPGA-SDC
• FPGA-SPICE
• Flow scripts
• Architecture library
• Cell library
• Documentation
• Regression tests
• Continous Integration (CI) scripts

Impact of the pull request

• Require a change on Quality of Results (QoR)
• Break back-compatibility. If so, please list who may be influenced.

[tangxifan]

@ganeshgore Check it out. I will merge soon. CI should be green.

[ganeshgore]

Worked for me. Thank you so much.