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[AMDGPU] Define constrained multi-dword scalar load instructions. #96161

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Merged
merged 3 commits into from
Jul 23, 2024
Merged

[AMDGPU] Define constrained multi-dword scalar load instructions. #96161

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a2deed4
[AMDGPU] Define constrained multi-dword scalar load instructions.
cdevadas Jun 20, 2024
f64ad28
skip _ec ld insn when data size is lesser or equal to 32.
cdevadas Jun 20, 2024
2850b4f
handle the pseudo instruction defs inside a multiclass.
cdevadas Jul 3, 2024
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21 changes: 17 additions & 4 deletions llvm/lib/Target/AMDGPU/SMInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -161,12 +161,25 @@ class SM_Discard_Pseudo <string opName, OffsetMode offsets>
let has_soffset = offsets.HasSOffset;
}

multiclass SM_Load_Pseudos<string op, RegisterClass baseClass,
RegisterClass dstClass, OffsetMode offsets> {
defvar opName = !tolower(op);
def "" : SM_Load_Pseudo <opName, baseClass, dstClass, offsets>;

// The constrained multi-dword load equivalents with early clobber flag at
// the dst operands. They are needed only for codegen and there is no need
// for their real opcodes.
if !gt(dstClass.RegTypes[0].Size, 32) then
let Constraints = "@earlyclobber $sdst",
PseudoInstr = op # offsets.Variant in
def "" # _ec : SM_Load_Pseudo <opName, baseClass, dstClass, offsets>;
}

multiclass SM_Pseudo_Loads<RegisterClass baseClass,
RegisterClass dstClass> {
defvar opName = !tolower(NAME);
def _IMM : SM_Load_Pseudo <opName, baseClass, dstClass, IMM_Offset>;
def _SGPR : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_Offset>;
def _SGPR_IMM : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_IMM_Offset>;
defm _IMM : SM_Load_Pseudos <NAME, baseClass, dstClass, IMM_Offset>;
defm _SGPR : SM_Load_Pseudos <NAME, baseClass, dstClass, SGPR_Offset>;
defm _SGPR_IMM : SM_Load_Pseudos <NAME, baseClass, dstClass, SGPR_IMM_Offset>;
}

multiclass SM_Pseudo_Stores<RegisterClass baseClass,
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