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[FirRegLowering] Add limit to number of ifs generated #8313

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Merged
merged 1 commit into from
Apr 2, 2025
Merged

[FirRegLowering] Add limit to number of ifs generated #8313

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21 changes: 18 additions & 3 deletions lib/Conversion/SeqToSV/FirRegLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,8 @@
#include "llvm/ADT/DenseSet.h"
#include "llvm/Support/Debug.h"

#include <deque>

using namespace circt;
using namespace hw;
using namespace seq;
Expand Down Expand Up @@ -396,6 +398,12 @@ FirRegLowering::tryRestoringSubaccess(OpBuilder &builder, Value reg, Value term,

void FirRegLowering::createTree(OpBuilder &builder, Value reg, Value term,
Value next) {
// If-then-else tree limit.
constexpr size_t limit = 1024;

// Count of emitted if-then-else ops.
size_t counter = 0;

// Get the fanout from this register before we build the tree. While we are
// creating the tree of if/else statements from muxes, we only want to turn
// muxes that are on the register's fanout into if/else statements. This is
Expand All @@ -405,9 +413,9 @@ void FirRegLowering::createTree(OpBuilder &builder, Value reg, Value term,
// enable.
auto firReg = term.getDefiningOp<seq::FirRegOp>();

SmallVector<std::tuple<Block *, Value, Value, Value>> worklist;
std::deque<std::tuple<Block *, Value, Value, Value>> worklist;
auto addToWorklist = [&](Value reg, Value term, Value next) {
worklist.push_back({builder.getBlock(), reg, term, next});
worklist.emplace_back(builder.getBlock(), reg, term, next);
};

auto getArrayIndex = [&](Value reg, Value idx) {
Expand All @@ -423,7 +431,9 @@ void FirRegLowering::createTree(OpBuilder &builder, Value reg, Value term,
OpBuilder::InsertionGuard guard(builder);
Block *block;
Value reg, term, next;
std::tie(block, reg, term, next) = worklist.pop_back_val();
std::tie(block, reg, term, next) = worklist.front();
worklist.pop_front();

builder.setInsertionPointToEnd(block);
if (areEquivalentValues(term, next))
continue;
Expand All @@ -433,10 +443,15 @@ void FirRegLowering::createTree(OpBuilder &builder, Value reg, Value term,
auto mux = next.getDefiningOp<comb::MuxOp>();
if (mux && mux.getTwoState() &&
reachableMuxes->isMuxReachableFrom(firReg, mux)) {
if (counter >= limit) {
builder.create<sv::PAssignOp>(term.getLoc(), reg, next);
continue;
}
addToIfBlock(
builder, mux.getCond(),
[&]() { addToWorklist(reg, term, mux.getTrueValue()); },
[&]() { addToWorklist(reg, term, mux.getFalseValue()); });
++counter;
continue;
}
// If the next value is an array creation, split the value into
Expand Down
6 changes: 3 additions & 3 deletions test/Dialect/Seq/firreg.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -606,8 +606,8 @@ hw.module @ArrayElements(in %a: !hw.array<2xi1>, in %clock: !seq.clock, in %cond
// CHECK-NEXT: %[[r2:.+]] = sv.array_index_inout %r[%true] : !hw.inout<array<2xi1>>, i1
// CHECK: sv.always posedge %clock {
// CHECK-NEXT: sv.if %cond {
// CHECK-NEXT: sv.passign %[[r1]], %1 : i1
// CHECK-NEXT: sv.passign %[[r2]], %0 : i1
// CHECK-NEXT: sv.passign %[[r1]], %1 : i1
// CHECK-NEXT: } else {
// CHECK-NEXT: }
// CHECK-NEXT: }
Expand Down Expand Up @@ -711,9 +711,9 @@ hw.module @NestedSubaccess(in %clock: !seq.clock, in %en_0: i1, in %en_1: i1, in
%31 = comb.mux bin %en_1, %27, %30 : !hw.array<3xi32>
%32 = hw.array_create %26, %24, %22 : i32
%33 = comb.mux bin %en_0, %31, %32 : !hw.array<3xi32>
// CHECK: %[[IDX1:.+]] = sv.array_index_inout %r[%addr_0] : !hw.inout<array<3xi32>>, i2
// CHECK: %[[IDX2:.+]] = sv.array_index_inout %r[%addr_1] : !hw.inout<array<3xi32>>, i2
// CHECK: %[[IDX3:.+]] = sv.array_index_inout %r[%addr_2] : !hw.inout<array<3xi32>>, i2
// CHECK: %[[IDX2:.+]] = sv.array_index_inout %r[%addr_1] : !hw.inout<array<3xi32>>, i2
// CHECK: %[[IDX1:.+]] = sv.array_index_inout %r[%addr_0] : !hw.inout<array<3xi32>>, i2
// CHECK: %[[IDX4:.+]] = sv.array_index_inout %r[%addr_3] : !hw.inout<array<3xi32>>, i2
// CHECK: sv.always posedge %clock {
// CHECK-NEXT: sv.if %en_0 {
Expand Down