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Mixed-size accesses #840
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3f3c9b6
AliasAnalysis.mayMix(MemoryCoreEvent,MemoryCoreEvent)
xeren 8ca166c
Tearing
xeren cb4a966
AnalysisTest.allKindsOfMixedSizeAccesses()
xeren bba372c
fixup! AliasAnalysis.mayMix(MemoryCoreEvent,MemoryCoreEvent)
xeren 9e5d5bd
fixup! Tearing
xeren b24a306
TransactionMarker
xeren d9a8288
SameTransaction
xeren 22700f1
teared events inherit tags from their original
xeren 67eae35
Track RMW after Tearing
xeren 343e786
Memory.isBigEndian()
xeren 190dc6b
Big Endian Tearing
xeren 706c464
Missing update of MemoryEvent.getAccessType() in Load and Store
xeren 5867d30
Remove inter-transaction program order
xeren 6953d44
fixup! SameTransaction
xeren 6dcfaa3
fixup! Track RMW after Tearing
xeren 8502499
More precise post-processing in InclusionBasedPointerAnalysis
xeren 8f38963
Remove unused array initializers in litmus tests
xeren 1538560
fixup! Tearing
xeren 2ab097a
Extend litmus grammar
xeren 62c2a9d
Detailed MSA information
xeren 3ff69de
Fix address arithmetics in tests from base i8 to i64, because the tes…
xeren 4ecbb32
Fix Mixed-size access detection in InclusionBasedPointerAnalysis
xeren 74e4964
Fix InclusionBasedPointerAnalysis.mayMixedSizeAccesses(MemoryCoreEven…
xeren 4ae26ab
ExpressionFactory.makeIntConcat(Expression,Expression)
xeren 9c48301
32-bit registers in VisitorLitmusAArch64
xeren 9b0f1a9
Fix teared stores always being 8-bit
xeren e08de66
Add support for 8-, 16- and 32-bit operations in AArch64 litmus tests
xeren 44b095e
Refactor
xeren 74e3033
Program.addInit(MemoryObject,int)
xeren 448bfe5
Tear initializations
xeren 1294220
LitmusAARCH64MSATest
xeren 9587591
cat and test adjustments
xeren 4d93091
fixup! Tear initializations
xeren 482b446
Different cat model
xeren c7322ed
TODO https://diy.inria.fr/mixed/mixed-aarch64/hardware.html#new
xeren 2f106f8
Tearing of final values
xeren 0a1c7d2
SameInstructionGraph
xeren 6c2156a
Litmus test collection
xeren 7053eea
fixup! Add support for 8-, 16- and 32-bit operations in AArch64 litmu…
xeren 7dff4d3
move aarch64-mixed.cat
xeren cac9850
typed declarations in AARCH64 litmus
xeren 1dd0fe5
LDP,STP
xeren 141c3ef
Fix LL/SC and more
xeren bc72b38
Added SWP(AL) operations to ARMv8 Litmus
ThomasHaas 934ee5c
Added Xchg event
ThomasHaas 7e24dbc
Option program.analysis.mixedSize
xeren 9a6f119
Ignore some MSA tests with too long in CI
xeren 224ba24
Fixed ThreadCreation initializing MemoryObjects with wrong types
ThomasHaas 03917b4
Add logging to Tearing.
ThomasHaas 9094f8a
Added IntConcat and IntExtract expressions that are used in Tearing
ThomasHaas fede31e
More precision w.r.t. ITE in InclusionBasedPointerAnalysis
xeren 7ea8ac1
More precision w.r.t. aggregates in InclusionBasedPointerAnalysis
xeren 08e3f24
Merge remote-tracking branch 'refs/remotes/origin/development' into m…
xeren 1299350
fixup! Merge remote-tracking branch 'refs/remotes/origin/development'…
xeren 44bc911
Updated aarch64-mixed-new.cat
ThomasHaas d6a81ba
Merge branch 'refs/heads/development' into mixed-sized-accesses
ThomasHaas 4dfff98
Fixed internal representation for IntExtract to have inclusive high-bit.
ThomasHaas e320c61
Merge branch 'refs/heads/add_bv_extract&concat' into mixed-sized-acce…
ThomasHaas d8407b7
Fixup
ThomasHaas 798070d
Added TODO
ThomasHaas 09cc562
Refinement now constructs its model of rmw directly from the encoding.
ThomasHaas aade24b
Opt-in MSA support
xeren a78c6b4
Insert Tearing into ProcessingManager
xeren 0cd1933
lockref benchmarks
xeren 3aee499
rename InstructionBoundary
xeren 11b2b57
Better MemCpy handling
xeren 426dd6b
Option program.processing.mixedSize
xeren 466f4f9
Fix AnalysisTest
xeren 85bba4b
Keep bytewise MemCpy without MSA
xeren 08c9d84
Merge branch 'refs/heads/development' into mixed-sized-accesses
ThomasHaas e83f759
Streamline lockref versions 1 and 2.
ThomasHaas 7fbb9c4
Fix MixedTest
xeren 6f9e294
Fix SpirvRacesTest
xeren 649b39e
Add amo, lxsx
xeren 1469d80
Move aarch64-mixed-new.cat into aarch64.cat
xeren 0ecc83c
Missing AARCH64-MIXED tests
xeren 9b2059b
fixup! Add amo, lxsx
xeren 855c091
fixup! Move aarch64-mixed-new.cat into aarch64.cat
xeren b2b3cb7
Merge remote-tracking branch 'refs/remotes/origin/development' into m…
xeren 59b7146
Missing unaligned tests
xeren 0d1c1f5
Proper lxsx in NativeRelationAnalysis
xeren 901638e
Merge remote-tracking branch 'refs/remotes/origin/development' into m…
xeren da092aa
fixup! Merge remote-tracking branch 'refs/remotes/origin/development'…
xeren c8a3b5f
fixup! Merge remote-tracking branch 'refs/remotes/origin/development'…
xeren ccabb0e
Ignore AARCH64-MIXED tests with OutOfMemory
xeren ad97839
fixup! Ignore AARCH64-MIXED tests with OutOfMemory
xeren 627af2f
Merge branch 'refs/heads/development' into mixed-sized-accesses
ThomasHaas c1a4bd2
Better lockref benchmarks
hernan-poncedeleon 052a7eb
Enable new lockref tests in CI
hernan-poncedeleon e8eabb3
Feedback implemented
hernan-poncedeleon 121dd3b
Arm instructions SWPB, SWPH
xeren e78c244
Merge remote-tracking branch 'origin/development' into mixed-sized-ac…
xeren 7f8fd7e
Special visualization of si
xeren 66fc931
Remove Tag.Armv8.MO_RX
xeren 1ba3e2e
Merge remote-tracking branch 'refs/remotes/origin/development' into m…
xeren bbd044e
Merge branch 'refs/heads/development' into mixed-sized-accesses
ThomasHaas e09212d
Add SameInstruction relation to LazyRelationAnalysis and LazyEncodeSets
ThomasHaas bc92d9c
Implement Feedback
xeren d84014a
Merge remote-tracking branch 'refs/remotes/origin/development' into m…
xeren 38f1f97
fixup! Implement Feedback
xeren eef0fb9
Merge remote-tracking branch 'refs/remotes/origin/development' into m…
xeren ed68c9f
fixup! Implement Feedback
xeren 049a056
mixed-local.c
xeren 8c9b8bb
MSA-aware MemToReg
xeren 7a07ffb
fixup! MSA-aware MemToReg
xeren a6a68e8
Merge remote-tracking branch 'refs/remotes/origin/development' into m…
xeren 2567cb4
Better naming of MemToReg registers
xeren 8e2eb77
Merge remote-tracking branch 'refs/remotes/origin/development' into m…
xeren 06da103
Tune Non-MSA AArch64 litmus tests
xeren 12b5f85
Merge branch 'refs/heads/development' into mixed-sized-accesses
ThomasHaas 19dcc9b
Fixup after merge
ThomasHaas 3d3cf5b
Add back accidentally removed encoding method.
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,103 @@ | ||
#include <stdatomic.h> | ||
#include <pthread.h> | ||
#include <assert.h> | ||
|
||
|
||
#ifndef NTHREADS | ||
#define NTHREADS 3 | ||
#endif | ||
|
||
// ========================================== | ||
// Spinlock | ||
// ========================================== | ||
|
||
struct spinlock_s { | ||
_Atomic(int32_t) lock; | ||
}; | ||
typedef struct spinlock_s spinlock_t; | ||
|
||
void await_for_lock(struct spinlock_s *l) | ||
{ | ||
while (atomic_load_explicit(&l->lock, memory_order_relaxed) != 0); | ||
return; | ||
} | ||
|
||
int try_get_lock(struct spinlock_s *l) | ||
{ | ||
int val = 0; | ||
return atomic_compare_exchange_strong_explicit(&l->lock, &val, 1, memory_order_acquire, memory_order_acquire); | ||
} | ||
|
||
void spin_lock(struct spinlock_s *l) | ||
{ | ||
do { | ||
await_for_lock(l); | ||
} while(!try_get_lock(l)); | ||
return; | ||
} | ||
|
||
void spin_unlock(struct spinlock_s *l) | ||
{ | ||
atomic_store_explicit(&l->lock, 0, memory_order_release); | ||
} | ||
|
||
// ========================================== | ||
// Lockref | ||
// ========================================== | ||
|
||
typedef struct { | ||
union { | ||
struct { | ||
atomic_int lock; | ||
int count; | ||
}; | ||
atomic_long lock_count; | ||
}; | ||
} lockref_t; | ||
|
||
void lockref_get(lockref_t *lockref) { | ||
long old_val = atomic_load_explicit(&lockref->lock_count, memory_order_relaxed); | ||
|
||
while (((lockref_t *)&old_val)->lock == 0) { | ||
long new_val = old_val; | ||
((lockref_t *)&new_val)->count++; | ||
if (atomic_compare_exchange_strong_explicit( | ||
&lockref->lock_count, &old_val, new_val, | ||
memory_order_relaxed, memory_order_relaxed)) { | ||
return; | ||
} | ||
} | ||
|
||
spin_lock(&lockref->lock); | ||
lockref->count++; | ||
spin_unlock(&lockref->lock); | ||
} | ||
|
||
// ========================================== | ||
// Main | ||
// ========================================== | ||
|
||
lockref_t my_lockref; | ||
|
||
void *thread_n(void *unsued) { | ||
|
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lockref_get(&my_lockref); | ||
|
||
return NULL; | ||
} | ||
|
||
int main() { | ||
|
||
pthread_t t[NTHREADS]; | ||
|
||
atomic_store(&my_lockref.lock_count, 0); | ||
|
||
for (int i = 0; i < NTHREADS; i++) | ||
pthread_create(&t[i], 0, thread_n, (void *)(size_t)i); | ||
|
||
for (int i = 0; i < NTHREADS; i++) | ||
pthread_join(t[i], 0); | ||
|
||
assert(my_lockref.count == NTHREADS); | ||
return 0; | ||
} |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,101 @@ | ||
#include <stdatomic.h> | ||
#include <pthread.h> | ||
#include <assert.h> | ||
|
||
#ifndef NTHREADS | ||
#define NTHREADS 3 | ||
#endif | ||
|
||
// ========================================== | ||
// Spinlock | ||
// ========================================== | ||
|
||
struct spinlock_s { | ||
_Atomic(int32_t) lock; | ||
}; | ||
typedef struct spinlock_s spinlock_t; | ||
|
||
void await_for_lock(struct spinlock_s *l) | ||
{ | ||
while (atomic_load_explicit(&l->lock, memory_order_relaxed) != 0); | ||
return; | ||
} | ||
|
||
int try_get_lock(struct spinlock_s *l) | ||
{ | ||
int val = 0; | ||
return atomic_compare_exchange_strong_explicit(&l->lock, &val, 1, memory_order_acquire, memory_order_acquire); | ||
} | ||
|
||
void spin_lock(struct spinlock_s *l) | ||
{ | ||
do { | ||
await_for_lock(l); | ||
} while(!try_get_lock(l)); | ||
return; | ||
} | ||
|
||
void spin_unlock(struct spinlock_s *l) | ||
{ | ||
atomic_store_explicit(&l->lock, 0, memory_order_release); | ||
} | ||
|
||
// ========================================== | ||
// Lockref | ||
// ========================================== | ||
|
||
struct lockref { | ||
union { | ||
_Atomic(int64_t) lock_count; | ||
struct { | ||
spinlock_t lock; | ||
_Atomic(int32_t) count; | ||
}; | ||
}; | ||
}; | ||
|
||
void lockref_get(struct lockref *lockref) { | ||
struct lockref old; | ||
|
||
old.lock_count = atomic_load_explicit(&lockref->lock_count, memory_order_relaxed); | ||
while (old.lock.lock == 0) { | ||
struct lockref new = old; | ||
new.count++; | ||
if (atomic_compare_exchange_strong_explicit(&lockref->lock_count, (int64_t *) &old.lock_count, new.lock_count, memory_order_relaxed, memory_order_relaxed)) { | ||
return; | ||
} | ||
} | ||
|
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spin_lock(&lockref->lock); | ||
lockref->count++; | ||
spin_unlock(&lockref->lock); | ||
} | ||
|
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// ========================================== | ||
// Main | ||
// ========================================== | ||
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struct lockref my_lockref; | ||
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void *thread_n(void *unsued) { | ||
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lockref_get(&my_lockref); | ||
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return NULL; | ||
} | ||
|
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int main() { | ||
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pthread_t t[NTHREADS]; | ||
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atomic_store(&my_lockref.lock_count, 0); | ||
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for (int i = 0; i < NTHREADS; i++) | ||
pthread_create(&t[i], 0, thread_n, (void *)(size_t)i); | ||
|
||
for (int i = 0; i < NTHREADS; i++) | ||
pthread_join(t[i], 0); | ||
|
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assert(my_lockref.count == NTHREADS); | ||
return 0; | ||
} |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,12 +1,18 @@ | ||
(* | ||
* The ARMv8 Application Level Memory Model. | ||
* The Armv8 Application Level Memory Model. | ||
* | ||
* See section B2.3 of the ARMv8 ARM: | ||
* This is a machine-readable, executable and formal artefact, which aims to be | ||
* the latest stable version of the Armv8 memory model. | ||
* If you have comments on the content of this file, please send an email to | ||
* [email protected], referring to version number: | ||
* 814a6fc1610ec1a24f2cbd178e171966375626ac | ||
* For a textual version of the model, see section B2.3 of the Armv8 ARM: | ||
* https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile | ||
* | ||
* Author: Will Deacon <[email protected]> | ||
* Author: Jade Alglave <[email protected]> | ||
* | ||
* Copyright (C) 2016, ARM Ltd. | ||
* Copyright (C) 2016-2020, Arm Ltd. | ||
* All rights reserved. | ||
* | ||
* Redistribution and use in source and binary forms, with or without | ||
|
@@ -44,10 +50,10 @@ | |
* location and then consequently defines the fr relation using co and | ||
* rf. | ||
*) | ||
include "cos.cat" | ||
include "coscat.cat" | ||
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(* | ||
* Include aarch64fences.cat so that barriers show up in generated diagrams. | ||
* Include aarch64fences.cat to define barriers. | ||
*) | ||
include "aarch64fences.cat" | ||
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||
|
@@ -79,32 +85,40 @@ flag ~empty (dmb.full | dmb.ld | dmb.st) \ | |
(* Coherence-after *) | ||
let ca = fr | co | ||
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(* Local read successor *) | ||
let lrs = [W]; (po-loc \ (po-loc;[W];po-loc)) ; [R] | ||
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(* Local write successor *) | ||
let lws = po-loc; [W] | ||
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(* Observed-by *) | ||
let obs = rfe | fre | coe | ||
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(* Dependency-ordered-before *) | ||
let dob = addr | data | ||
let dob = (addr | data) | ||
| ctrl; [W] | ||
| (ctrl | (addr; po)); [ISB]; po; [R] | ||
| addr; po; [W] | ||
| (ctrl | data); coi | ||
| (addr | data); rfi | ||
| (addr | data); lrs | ||
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(* Atomic-ordered-before *) | ||
let aob = rmw | ||
| [range(rmw)]; rfi; [A | Q] | ||
| [range(rmw)]; lrs; [A | Q] | ||
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(* Barrier-ordered-before *) | ||
let bob = po; [dmb.full]; po | ||
| po; ([A];amo;[L]); po | ||
| [L]; po; [A] | ||
| [R]; po; [dmb.ld]; po | ||
| [A | Q]; po | ||
| [W]; po; [dmb.st]; po; [W] | ||
| po; [L] | ||
| po; [L]; coi | ||
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(* Locally-ordered-before *) | ||
let lob = lws; si | dob | aob | bob | ||
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(* Ordered-before *) | ||
let ob = obs | dob | aob | bob | ||
let ob = obs; si | lob | ||
|
||
(* Internal visibility requirement *) | ||
acyclic po-loc | ca | rf as internal | ||
|
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I don't see the point of keeping both variants (specially since according to Thomas both generated the same dat3m IR). This just make it more confusing for people trying to navigate over the benchmarks in the repo with no clear benefit.
I added another method for the API, refactor the code and created some more interesting examples. I would simply remove
lockref1
andlockrref2
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The two versions are very different in terms of LLVM IR. The fact that we create (almost) the same internal IR is not obvious which makes it a valuable benchmark to evaluate our processing pipeline.
I don't think we need the two versions as unit tests, but I would like to keep them around for manual testing, i.e., inspection of logging outputs. We could have a seperate directory for such benchmarks.