sdgemm micro-kernel for the SG2042 RISC-V processor

[evenieri]

Hi, my name is Emanuele and I am a research fellow at the University of Bologna. In our lab, we are exploring the capabilities of emerging hardware platforms, including the SG2042 RISC-V processor. As part of this effort, also involving a student project, we selected BLIS.

As you may know, the SG2042 supports RVV 0.7.1, whereas BLIS currently includes kernels targeting RVV 1.0. Our goal was to make the RVV kernels compatible with the SG2042 using GCC 14. To achieve this, we performed a set of adaptations to target the xtheadvector machine architecture. Following an initial port, we conducted performance analysis and optimized the register grouping for this processor's register file, significantly reducing instruction count in the sdgemm micro-kernel.

Using HPL as a benchmark, we observed a 49% performance improvement over the standard BLIS RVV sdgemm micro-kernel.

Following your contribution guidelines, we integrated our work as a new configuration family: rvv_sg2042, which is fully compatible with GCC 14. The sdgemm micro-kernel has been optimized, while czgemm was adapted to compile and run correctly, though not performance-tuned.

We hope this contribution could be interesting for the BLIS community as well as the RISC-V community.

[evenieri]

Some insights of our work, that include the activity on BLIS can be seen here:
https://arxiv.org/abs/2503.18543