Add/Test AXI-Lite/AXI support. #1

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Closed

6 tasks done

enjoy-digital opened this issue Dec 4, 2023 · 1 comment

Owner

enjoy-digital commented Dec 4, 2023 •

edited

Loading

The first interconnect that will be converted to 64-bit addressing support is the Wishbone Interconnect. This will allow the following PoC:

With 64-bit addressing support in place for Wishbone, it will be possible to progressively add and test AXI-Lite/AXI support:

UARTBone (Wishbone) <-> AXI-Lite-Interconnect <-> Wishbone SRAMs.
UARTBone (Wishbone) <-> AXI-Lite-Interconnect <-> AXI-Lite SRAMs.
UARTBone (Wishbone) <-> AXI-Full-Interconnect <-> Wishbone SRAMs.
UARTBone (Wishbone) <-> AXI-Full-Interconnect <-> AXI-Lite SRAMs.
UARTBone (Wishbone) <-> AXI-Lite-Interconnect <-> LiteDRAM (Wishbone or AXI port).
UARTBone (Wishbone) <-> AXI-Full-Interconnect <-> LiteDRAM (Wishbone or AXI port).

enjoy-digital mentioned this issue

Add 64-bit addressing support. enjoy-digital/litex#1844

Closed

6 tasks

Owner Author

enjoy-digital commented Dec 8, 2023

This is now done and tested.

enjoy-digital closed this as completed

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment