Add 64-bit addressing support.

[enjoy-digital]

For some specific cases, it would be useful to support 64-bit addressing, for example to be able to map > 1GB of DRAM to the SoC.

• Identify/Remove limitation on SoC/Wishbone modules.
• Identify/Remove limitation on AXI(-Lite) modules. (Add/Test AXI-Lite/AXI support. litex_64bit_addressing_test#1)
• Identify/Remove limitation on LiteX-Server / Etherbone communication.
• Identify/Remove limitation on UARTBone.
• Prepare a PoC with > 1GB of DRAM fully mapped to a 64-bit SoC and demonstrate access to it over UARTBone (Prepare PoC on Arty/KCU105 and verify > 1GB access. litex_64bit_addressing_test#2)
• Identify a CPU that would be able to address more than 32-bit space and prepare a 64-bit addressing demo with it. Would be interesting to see if that would be possible with NaxRiscv.

[enjoy-digital]

Specific repo for the tests/PoC and specific scripts/targets has been created here: https://github.com/enjoy-digital/litex_64bit_addressing_test

[enjoy-digital]

@kgugala: For info, using an AXI-Lite/AXI bus standard is now also functionnal in 64-bit (with upstream LiteX). For now we did the test on an Arty and only 256MB of RAM, but we'll now do the test with a board with > 1GB of RAM.

[enjoy-digital]

This is now implemented. Access has been tested over UARTBone in https://github.com/enjoy-digital/litex_64bit_addressing_test repo. In the future we'll also do some test with CPUs able to address 64-bit but we can now close this issue.