asm: Add Load-Acquire and Store-Release instructions #1751
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This commit adds proper stringification for the Load-Acquire and Store-Release instructions as well as functions to generate these instructions. Signed-off-by: Dylan Reimerink <[email protected]>
dylandreimerink
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Apr 13, 2025
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| // LoadAcquire emits an atomic load with acquire semantics. | ||
| func LoadAcquire(dst, src Register, offset int16, size Size) Instruction { | ||
| return Instruction{ | ||
| OpCode: StoreXAddOp(size), // We use Store here, for a Load, this is a quirk of the ISA | ||
| Dst: dst, | ||
| Src: src, | ||
| Offset: offset, | ||
| Constant: int64(LoadAcquireAtomicFlag), | ||
| } | ||
| } | ||
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| // StoreRelease emits an atomic store with release semantics. | ||
| func StoreRelease(dst, src Register, offset int16, size Size) Instruction { |
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I kept the descriptions on these brief for now. Not sure how much context we need to give the user about what these instructions do.
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This PR adds proper stringification for the Load-Acquire and Store-Release instructions added in v6.15 as well as functions to generate these instructions.
These new instructions will fall under the BPF ISAv4. They are atomic load/store instructions with a "memory order", which seems to be best explained here.
The acquire-release semantics surrounding these instructions provide rules for the non-atomic reads and writes around these instructions can and cannot be reordered. See the kernel lore linked in the original issue for details.
The way they decided to encode these new instructions is to use the
imm/Constantbit of the BPF instruction to further special theBPF_ATOMIC | BPF_STX/StXClass | XAddModeopcode. Interestingly, this means that the "store" class now actually can be a load depending on itsimm/Constantvalue, which forces us to do some special casing in our string formatting logic.Fixes: #1750