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Description
Incorrect complement of partly filled enums
Parsing SystemVerilog code (a.sv):
typedef enum logic [1:0] {
A = 3, B = 0, C, D
} state_t;
module top(input clk, output z);
state_t state = A;
always @(posedge clk) begin
case (state)
A: state <= B;
B: state <= C;
C: state <= D;
default: state <= A;
endcase
end
assign z = (state == B);
endmodule
with surelog -parse -elabuhdm a.sv
, results in UHDM Tree that sets both enum
values A
and D
to 3
. Below is UHDM Tree fragment responsible for enum
.
|vpiEnumConst:
\_enum_const: (A), line:2:5, endln:2:10
|vpiParent:
\_enum_typespec: (state_t), line:1:1, endln:3:11
|vpiName:A
|UINT:3
|vpiDecompile:3
|vpiSize:64
|vpiEnumConst:
\_enum_const: (B), line:2:12, endln:2:17
|vpiParent:
\_enum_typespec: (state_t), line:1:1, endln:3:11
|vpiName:B
|UINT:0
|vpiDecompile:0
|vpiSize:64
|vpiEnumConst:
\_enum_const: (C), line:2:19, endln:2:20
|vpiParent:
\_enum_typespec: (state_t), line:1:1, endln:3:11
|vpiName:C
|INT:2
|vpiDecompile:2
|vpiSize:2
|vpiEnumConst:
\_enum_const: (D), line:2:22, endln:2:23
|vpiParent:
\_enum_typespec: (state_t), line:1:1, endln:3:11
|vpiName:D
|INT:3
|vpiDecompile:3
|vpiSize:2
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