Skip to content

REFACTOR: pathlib refactor primitives_circuit.py #6024

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 4 commits into from
Apr 10, 2025
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
1 change: 1 addition & 0 deletions doc/changelog.d/6024.miscellaneous.md
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
pathlib refactor primitives_circuit.py
29 changes: 14 additions & 15 deletions src/ansys/aedt/core/modeler/circuits/primitives_circuit.py
Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,6 @@
# SOFTWARE.

import math
import os
from pathlib import Path
import secrets
import warnings
Expand Down Expand Up @@ -488,7 +487,7 @@

Parameters
----------
input_file : str
input_file : str or :class:`pathlib.Path`
Full path to the Touchstone file.
model_name : str, optional
Name of the model. The default is ``None``.
Expand All @@ -508,12 +507,12 @@
"""

if not model_name:
model_name = os.path.splitext(os.path.basename(input_file))[0]
model_name = Path(Path(input_file).name).stem
if "." in model_name:
model_name = model_name.replace(".", "_")
if model_name in list(self.omodel_manager.GetNames()):
model_name = generate_unique_name(model_name, n=2)
num_terminal = int(os.path.splitext(input_file)[1].lower().strip(".sp"))
num_terminal = int(Path(input_file).suffix.lower().strip(".sp"))

port_names = []
with open_file(input_file, "r") as f:
Expand All @@ -527,8 +526,8 @@
image_subcircuit_path = ""
bmp_file_name = ""
if show_bitmap:
image_subcircuit_path = os.path.join(self._app.desktop_install_dir, "syslib", "Bitmaps", "nport.bmp")
bmp_file_name = os.path.basename(image_subcircuit_path)
image_subcircuit_path = Path(self._app.desktop_install_dir) / "syslib" / "Bitmaps" / "nport.bmp"
bmp_file_name = Path(image_subcircuit_path).name

if not port_names:
port_names = ["Port" + str(i + 1) for i in range(num_terminal)]
Expand All @@ -547,13 +546,13 @@
"Description:=",
"",
"ImageFile:=",
image_subcircuit_path,
str(image_subcircuit_path),
"SymbolPinConfiguration:=",
0,
["NAME:PortInfoBlk"],
["NAME:PortOrderBlk"],
"filename:=",
input_file,
str(input_file),
"numberofports:=",
num_terminal,
"sssfilename:=",
Expand Down Expand Up @@ -662,7 +661,7 @@
"InfoHelpFile:=",
"",
"IconFile:=",
bmp_file_name,
str(bmp_file_name),
"Library:=",
"",
"OriginalLocation:=",
Expand Down Expand Up @@ -765,7 +764,7 @@
"""

if not model_name:
model_name = os.path.splitext(os.path.basename(input_file))[0]
model_name = Path(Path(input_file).name).stem
if "." in model_name:
model_name = model_name.replace(".", "_")
if model_name in list(self.omodel_manager.GetNames()):
Expand Down Expand Up @@ -1681,18 +1680,18 @@
def _index_components(self, library_path=None):
if library_path:
sys_files = recursive_glob(library_path, "*.aclb")
root = os.path.normpath(library_path).split(os.path.sep)[-1]
root = Path(library_path).name

Check warning on line 1683 in src/ansys/aedt/core/modeler/circuits/primitives_circuit.py

View check run for this annotation

Codecov / codecov/patch

src/ansys/aedt/core/modeler/circuits/primitives_circuit.py#L1683

Added line #L1683 was not covered by tests
else:
sys_files = recursive_glob(os.path.join(self._app.syslib, self._component_manager.design_libray), "*.aclb")
root = os.path.normpath(self._app.syslib).split(os.path.sep)[-1]
sys_files = recursive_glob(Path(self._app.syslib) / self._component_manager.design_libray, "*.aclb")
root = Path(self._app.syslib).name
for file in sys_files:
comps1 = load_keyword_in_aedt_file(file, "DefInfo")
comps2 = load_keyword_in_aedt_file(file, "CompInfo")
comps = comps1.get("DefInfo", {})
comps.update(comps2.get("CompInfo", {}))
for compname, comp_value in comps.items():
root_name, ext = os.path.splitext(os.path.normpath(file))
full_path = root_name.split(os.path.sep)
root_name = str(Path(file).with_suffix(""))
full_path = list(Path(root_name).parts)
id = full_path.index(root) + 1
if self._component_manager.design_libray in full_path[id:]:
id += 1
Expand Down