feat(Examples,CMSIS,PeriphDrivers): Update HART UART with new transmit features and fixes for MAX32675 and MAX32680 #600
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Noted TX_OB (One Byte Remaining) flag and enable missing from ME16 uart_regs.h. Added and conformed to ME55 naming. Also added to all uart revb devices: ME12, ME15, ME16, ME17, ME18, ME20. Already in ME55.
HART UART: Feature Update SAP, interrupt TX Initial implementation of interrupt driven transmitter. And SAP (Service Access Points) to comply with HART TPDLL Specification. AFE: Add Revision IDs for Rev A Silicon Note these revision IDS are for ME15. HART UART: Correct hart_uart_transmit_irq() Was not properly calculating remaining bytes to send. Also added some length checks to hart_uart_send* AFE: Initial addition of afe_timer AFE Timer: Basic Functionality working HART UART: Now using afe_timer_delay instead of MXC_Delay Also reset transmit index for every transmission. AFE Timer: Fix AFE_TMR_Start_16, use offset AFE Timer: Change to complete Boolean Was comparing cnt to cmp registers, but cnt appears to roll over, so this was not working properly. AFE: Switch to afe_timer. Update Reset Timeout Check Also modified masks etc. for pre_reset change reset checks. Note: MXC_Delay was used previously, but due to its behavior it was not reliable to use. It only handles one delay at a time, and doesn't callback for short delays. Caused a lot of odd behaviors here. AFE, HART: Moved afe_load_trims to main Due to changed behaviors in recent silicon, now it makes more sense to have afe_load_trims in main instead of SysInit. Need to handle potential errors etc. And need to pass a valid timer instance to the AFE as well. HART: Actually enable RX Errors. Fix error flag check for FIFO overrun HART: Fixes to SAP interface Tests passing. HART_UART: Example shows errors and SAPs HART: Replace old hart_uart_send with non-blocking Removed old, and renamed new. HART: Cleanup FIXMES, Doxygen HART: Rename functions for consistency Per GitHub code review comments. HART UART Example: Init before banners etc. Improved behavior with Segger Debug adapter. AFE: Use GCR define for AFE RESET bit HART: Some config changes to better match uPython Moved all uart config into hart_uart_init function. This better matches downstream uPython implementations. However, unable to completely match Many of the uart config such as threshold, data size, stop bits etc. are already set by default but these show it explicitly. AFE, HART: Update other examples using AFE New initialization is done in main instead of SystemInit. AFE, HART: Formatter updates HART: Linter updates
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Added Jake and Sihyung regarding the Action failure. |
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@ozersa This includes changes based on your comments from previous Pull Request. I also added some of the downstream changes from the uPython port you previously mentioned as well. I elected to not include the setup with specific frequency, and clock divider params as, these were passed to MXC_UART_RevB_SetFrequency_Custom which doesn't exist in the current SDK. I also did not bring in the clkdiv param to enable_hart_clock. This is complicated by the MAX32680 having to use the Pulse Train for clock gen and doesn't map directly to clock divider. So I left it alone for now. |
jdk-maxim
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API Change
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/generate-register-files |
sihyung-maxim
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mbayraker
approved these changes
Jun 7, 2023
sihyung-maxim
approved these changes
Jun 13, 2023
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Fixed the Verify_Register workflow. Nothing wrong on your part, the machine that hosts the workflow's runner never reran the SVD scripts when checking with your register files. Weird bug, but I'll fix it in another PR. I'll merge in this PR once the workflows all finish. |
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Add additional requested features to HART UART.
Also a couple of incidental fixes for TX_OB, ME16 Timer Warnings, and Change to GPIO IRQ handlers.