ME15: Added LP OVR Feature Support. (#441)

* ME15: Added LP OVR Feature Support.

* Updating lp_me15.c for clang-formatting error.

* Clang-formatted lp_me15.c locally.

* ME16 LP: Updated OVR enum values.

* ME16 LP: Fixed function prototype.

* LP OVR: Added note in doxygen header for peripheral reset.

* LP OVR: Removed @note from doxygen.

* LP ME15: Ensure appropriate control bit is set for OVR.

* Fixed syntax error.

Author: sihyung-maxim

Libraries/PeriphDrivers/Include/MAX32670/lp.h

@@ -60,9 +60,12 @@ extern "C" {
 
 /**
  * @brief   Enumeration type for voltage selection
- *
  */
-typedef enum { MXC_LP_V0_9 = 0, MXC_LP_V1_0, MXC_LP_V1_1 } mxc_lp_ovr_t;
+typedef enum {
+    MXC_LP_OVR_0_9 = MXC_S_PWRSEQ_LPCN_OVR_0_9V, /**< OVR 0.9V */
+    MXC_LP_OVR_1_0 = MXC_S_PWRSEQ_LPCN_OVR_1_0V, /**< OVR 1.0V */
+    MXC_LP_OVR_1_1 = MXC_S_PWRSEQ_LPCN_OVR_1_1V, /**< OVR 1.1V */
+} mxc_lp_ovr_t;
 
 /**
  * @brief   Enumeration type for PM Mode
@@ -103,11 +106,14 @@ void MXC_LP_EnterStorageMode(void);
 void MXC_LP_EnterShutDownMode(void);
 
 /**
- * @brief      Set ovr bits to set the voltage the micro will run at.
+ * @brief      Sets the operating voltage for the device. The caller must perform the peripheral reset after 
+ *             calling this function.
  *
  * @param[in]  ovr   The ovr options are only 0.9V, 1.0V, and 1.1V use enum mxc_lp_ovr_t
+ * 
+ * @return     Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 
  */
-void MXC_LP_SetOVR(mxc_lp_ovr_t ovr);
+int MXC_LP_SetOVR(mxc_lp_ovr_t ovr);
 
 /**
  * @brief      Enable retention regulator

Libraries/PeriphDrivers/Include/MAX32675/lp.h

@@ -60,9 +60,12 @@ extern "C" {
 
 /**
  * @brief   Enumeration type for voltage selection
- *
  */
-typedef enum { MXC_LP_V0_9 = 0, MXC_LP_V1_0, MXC_LP_V1_1 } mxc_lp_ovr_t;
+typedef enum {
+    MXC_LP_OVR_0_9 = MXC_S_PWRSEQ_LPCN_OVR_0_9V, /**< OVR 0.9V */
+    MXC_LP_OVR_1_0 = MXC_S_PWRSEQ_LPCN_OVR_1_0V, /**< OVR 1.0V */
+    MXC_LP_OVR_1_1 = MXC_S_PWRSEQ_LPCN_OVR_1_1V, /**< OVR 1.1V */
+} mxc_lp_ovr_t;
 
 /**
  * @brief   Enumeration type for PM Mode
@@ -103,11 +106,14 @@ void MXC_LP_EnterStorageMode(void);
 void MXC_LP_EnterShutDownMode(void);
 
 /**
- * @brief      Set ovr bits to set the voltage the micro will run at.
+ * @brief      Sets the operating voltage for the device. The caller must perform the peripheral reset after 
+ *             calling this function.
  *
  * @param[in]  ovr   The ovr options are only 0.9V, 1.0V, and 1.1V use enum mxc_lp_ovr_t
+ * 
+ * @return     Success/Fail, see \ref MXC_Error_Codes for a list of return codes. 
  */
-void MXC_LP_SetOVR(mxc_lp_ovr_t ovr);
+int MXC_LP_SetOVR(mxc_lp_ovr_t ovr);
 
 /**
  * @brief      Enable retention regulator

Libraries/PeriphDrivers/Source/LP/lp_me15.c

@@ -33,8 +33,10 @@
 
 #include "mxc_device.h"
 #include "mxc_assert.h"
+#include "mxc_errors.h"
 #include "mxc_sys.h"
 #include "gcr_regs.h"
+#include "flc_regs.h"
 #include "lp.h"
 
 void MXC_LP_EnterSleepMode(void)
@@ -102,9 +104,94 @@ void MXC_LP_EnterShutDownMode(void)
     // Should never reach this line - device will reset on exit from shutdown mode.
 }
 
-void MXC_LP_SetOVR(mxc_lp_ovr_t ovr)
+int MXC_LP_SetOVR(mxc_lp_ovr_t ovr)
 {
-    //not supported yet
+    uint32_t current_clock, div;
+    int error;
+
+    // Ensure part is operating from internal LDO for core power
+    if (MXC_PWRSEQ->lpcn & MXC_F_PWRSEQ_LPCN_LDO_DIS) {
+        return E_BAD_STATE;
+    }
+
+    // Select the 8KHz nanoring (no guarantee 32KHz is attached) as system clock source
+    current_clock = MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL;
+    if (current_clock == MXC_SYS_CLOCK_IPO) {
+        error = MXC_SYS_Clock_Select(MXC_SYS_CLOCK_INRO);
+        if (error != E_NO_ERROR) {
+            return error;
+        }
+    }
+
+    // Set flash wait state for any clock so its not to low after clock changes.
+    MXC_GCR->memctrl = (MXC_GCR->memctrl & ~(MXC_F_GCR_MEMCTRL_FWS)) |
+                       (0x5UL << MXC_F_GCR_MEMCTRL_FWS_POS);
+
+    // Set the OVR bits
+    //  The OVR enums in mxc_lp_ovr_t equals to their appropriate register setting.
+    MXC_SETFIELD(MXC_PWRSEQ->lpcn, MXC_F_PWRSEQ_LPCN_OVR, ovr);
+
+    // Set LVE bit
+    if (ovr == MXC_LP_OVR_0_9) {
+        MXC_FLC0->ctrl |= MXC_F_FLC_CTRL_LVE;
+
+    } else {
+        MXC_FLC0->ctrl &= ~(MXC_F_FLC_CTRL_LVE);
+    }
+
+    // Revert the clock to original state if it was IPO
+    if (current_clock == MXC_SYS_CLOCK_IPO) {
+        error = MXC_SYS_Clock_Select(MXC_SYS_CLOCK_IPO);
+        if (error != E_NO_ERROR) {
+            return error;
+        }
+    }
+
+    // Update SystemCoreClock variable
+    SystemCoreClockUpdate();
+
+    // Get the clock divider
+    div = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_DIV) >> MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS;
+
+    // Set Flash Wait States
+    if (ovr == MXC_LP_OVR_0_9) {
+        if (div == 0) {
+            MXC_GCR->memctrl = (MXC_GCR->memctrl & ~(MXC_F_GCR_MEMCTRL_FWS)) |
+                               (0x2UL << MXC_F_GCR_MEMCTRL_FWS_POS);
+
+        } else {
+            MXC_GCR->memctrl = (MXC_GCR->memctrl & ~(MXC_F_GCR_MEMCTRL_FWS)) |
+                               (0x1UL << MXC_F_GCR_MEMCTRL_FWS_POS);
+        }
+
+    } else if (ovr == MXC_LP_OVR_1_0) {
+        if (div == 0) {
+            MXC_GCR->memctrl = (MXC_GCR->memctrl & ~(MXC_F_GCR_MEMCTRL_FWS)) |
+                               (0x2UL << MXC_F_GCR_MEMCTRL_FWS_POS);
+
+        } else {
+            MXC_GCR->memctrl = (MXC_GCR->memctrl & ~(MXC_F_GCR_MEMCTRL_FWS)) |
+                               (0x1UL << MXC_F_GCR_MEMCTRL_FWS_POS);
+        }
+
+    } else {
+        if (div == 0) {
+            MXC_GCR->memctrl = (MXC_GCR->memctrl & ~(MXC_F_GCR_MEMCTRL_FWS)) |
+                               (0x4UL << MXC_F_GCR_MEMCTRL_FWS_POS);
+
+        } else if (div == 1) {
+            MXC_GCR->memctrl = (MXC_GCR->memctrl & ~(MXC_F_GCR_MEMCTRL_FWS)) |
+                               (0x2UL << MXC_F_GCR_MEMCTRL_FWS_POS);
+
+        } else {
+            MXC_GCR->memctrl = (MXC_GCR->memctrl & ~(MXC_F_GCR_MEMCTRL_FWS)) |
+                               (0x1UL << MXC_F_GCR_MEMCTRL_FWS_POS);
+        }
+    }
+
+    // Caller must perform peripheral reset
+
+    return E_NO_ERROR;
 }
 
 void MXC_LP_RetentionRegEnable(void)