Verilog HDL Module Instantiation error at hx8kdemo.v(65)

[YapWC]

Hi there,

Currently I am trying to synthesize PICORV32 onto DE0 Nano FPGA using Quartus Prime Lite.

I have no problem synthesizing with synth_area_top.v it was successful.

However when it comes to hx8kdemo.v I get an error as shown below.

Verilog HDL Module Instantiation error at hx8kdemo.v(65): cannot elaborate array of instances because the declaration for the instantiated module has not been analyzed.

I am not sure if I missed adding any files into the project that caused so? Appreciate if anyone could provide me a guide in this case.

[jix]

The "hx8k" refers to the Lattice iCE40HX-8k FPGA and the error you get is for the SB_IO module which is an IO primitive of that FPGA family. When targeting an Altera/Intel FPGA you would need to replace it with the corresponding vendor specific primitive.