out of tree build #307
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out of tree build #307
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this RISC-V worked well both on its own and as a support mechanism for testing DSP examples before. I'm curious is our way of using BSRAM so crooked or is this an innovation in yosys that requires a different approach to BSRAM? :) 2.9. Executing MEMORY_LIBMAP pass (mapping memories to cells).
found attribute 'ram_style = block' on memory top.CPU.RegisterBank, forced mapping to block RAM
mapping memory top.CPU.RegisterBank via $__GOWIN_SDP_
make: *** [Makefile.himbaechel:319: femto-riscv-16-tangnano4k-synth.json] Segmentation fault (сделан дамп памяти)Complete log c.log |
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If it reproduces locally we could bisect the yosys commit that broke it and report upstream. |
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done YosysHQ/yosys#4883 |
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