Skip to content
View WangSibothunder's full-sized avatar
🙃
I may be slow to respond.
🙃
I may be slow to respond.

Organizations

@NEUQ-CS @BCIC-LAB

Block or report WangSibothunder

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
WangSibothunder/README.md

Hello

my Chinese name is 王思博, and you can also call me Thunder Wang

BCIC-LAB members

  • 🔭 I’m currently a college student of Northeastern University
  • 🌱 I’m currently learning Electrical Engineer
  • 📫 How to reach me: [email protected] is my personal account

currently ,I am interested in the IC design and have to make a low-power and efficienct xpu,also called hardware accelerate.

Pinned Loading

  1. WangSibothunder WangSibothunder Public

    My Personal Reposity

    1

  2. LAB-Web LAB-Web Public

    HTML

  3. NEUQ-CS/manual NEUQ-CS/manual Public

    生產分支預覽:https://manual.caiyi1.me/

    C# 2 9

  4. BCIC-LAB/.github BCIC-LAB/.github Public

    a brief introdcation of the Brain-Computer Interface and Hardware Acceleration Laboratory

  5. Booth-with-systolic-array-implemt Booth-with-systolic-array-implemt Public

    This is one implement of the hardware design of a systolic array using the boothPE instead of *.I ve studied VERILOG for 2.5month,and this implement mabye naive.I want to upgrade it in this year

    Verilog 1