GitHub - FaezehShakouri/RISC-Processor-Verilog: A RISC processor in verilog

Name	Name	Last commit message	Last commit date
Latest commit History 19 Commits
iseconfig	iseconfig
ALU.cmd_log	ALU.cmd_log
ALU.v	ALU.v
ALU_Control.cmd_log	ALU_Control.cmd_log
ALU_Control.v	ALU_Control.v
Adder.cmd_log	Adder.cmd_log
Adder.lso	Adder.lso
Adder.v	Adder.v
Adder_2.cmd_log	Adder_2.cmd_log
Adder_2.lso	Adder_2.lso
Adder_2.v	Adder_2.v
And.cmd_log	And.cmd_log
And.lso	And.lso
And.v	And.v
Control_Unit.cmd_log	Control_Unit.cmd_log
Control_Unit.lso	Control_Unit.lso
Control_Unit.v	Control_Unit.v
Data_Memory.cmd_log	Data_Memory.cmd_log
Data_Memory.lso	Data_Memory.lso
Data_Memory.v	Data_Memory.v
Decode.cmd_log	Decode.cmd_log
Decode.lso	Decode.lso
Decode.v	Decode.v
Decode_summary.html	Decode_summary.html
EX_MEM.cmd_log	EX_MEM.cmd_log
EX_MEM.lso	EX_MEM.lso
EX_MEM.v	EX_MEM.v
Execute.cmd_log	Execute.cmd_log
Execute.lso	Execute.lso
Execute.v	Execute.v
ID-EX.v	ID-EX.v
ID_EX.cmd_log	ID_EX.cmd_log
ID_EX.lso	ID_EX.lso
ID_EX.v	ID_EX.v
IF-ID.v	IF-ID.v
IF_ID.cmd_log	IF_ID.cmd_log
IF_ID.lso	IF_ID.lso
Instr_Fetch.lso	Instr_Fetch.lso
Instr_Fetch.v	Instr_Fetch.v
Instr_Fetch_Test.v	Instr_Fetch_Test.v
Instruction_Cache.cmd_log	Instruction_Cache.cmd_log
Instruction_Cache.lso	Instruction_Cache.lso
Instruction_Cache.v	Instruction_Cache.v
Instruction_Memory.lso	Instruction_Memory.lso
Instruction_Memory.v	Instruction_Memory.v
Instruction_Memory_Test.v	Instruction_Memory_Test.v
Instruction_Memory_Test_isim_beh2.wdb	Instruction_Memory_Test_isim_beh2.wdb
MEM_WB.cmd_log	MEM_WB.cmd_log
MEM_WB.v	MEM_WB.v
MIPS.cmd_log	MIPS.cmd_log
MIPS.lso	MIPS.lso
MIPS.v	MIPS.v
MUX_3_bit.cmd_log	MUX_3_bit.cmd_log
MUX_3_bit.lso	MUX_3_bit.lso
MUX_3_bit.v	MUX_3_bit.v
Memory.cmd_log	Memory.cmd_log
Memory.lso	Memory.lso
Memory.v	Memory.v
Mux_16_to_1.v	Mux_16_to_1.v
Mux_16_to_1_summary.html	Mux_16_to_1_summary.html
Mux_2_1.cmd_log	Mux_2_1.cmd_log
Mux_2_1.sym	Mux_2_1.sym
Mux_2_1.v	Mux_2_1.v
Mux_2_To_1.v	Mux_2_To_1.v
Mux_2_To_1_Test.v	Mux_2_To_1_Test.v
Mux_2_To_1_Test_isim_beh.wdb	Mux_2_To_1_Test_isim_beh.wdb
PC.v	PC.v
PC_Test.v	PC_Test.v
PC_Test_isim_beh1.wdb	PC_Test_isim_beh1.wdb
README.md	README.md
RISC_Processor.gise	RISC_Processor.gise
RISC_Processor.xise	RISC_Processor.xise
Register_File.cmd_log	Register_File.cmd_log
Register_File.lso	Register_File.lso
Register_File.v	Register_File.v
Register_File_envsettings.html	Register_File_envsettings.html
Register_File_summary.html	Register_File_summary.html
Sign_Extend.cmd_log	Sign_Extend.cmd_log
Sign_Extend.lso	Sign_Extend.lso
Sign_Extend.v	Sign_Extend.v
Sign_Extend_summary.html	Sign_Extend_summary.html
Write_Back.cmd_log	Write_Back.cmd_log
Write_Back.lso	Write_Back.lso
Write_Back.v	Write_Back.v
alu_control_test.v	alu_control_test.v
alu_control_test_isim_beh1.wdb	alu_control_test_isim_beh1.wdb
control_unit_test.v	control_unit_test.v
data_memory.txt	data_memory.txt
data_memory_test.v	data_memory_test.v
data_memory_test_isim_beh2.wdb	data_memory_test_isim_beh2.wdb
decode_test.v	decode_test.v
decode_test_isim_beh.exe	decode_test_isim_beh.exe
decode_test_isim_beh.wdb	decode_test_isim_beh.wdb
decode_test_isim_beh2.wdb	decode_test_isim_beh2.wdb
execute_test.v	execute_test.v
execute_test_isim_beh1.wdb	execute_test_isim_beh1.wdb
fuse.xmsgs	fuse.xmsgs
fuseRelaunch.cmd	fuseRelaunch.cmd
instruction.txt	instruction.txt
instruction_mem.txt	instruction_mem.txt

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