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Merged
merged 4 commits into from
May 27, 2021
Merged

STM32L5 update drivers version to CUBE V1.4.0 #14687

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276eefd
STM32L5 update drivers version to CUBE V1.4.0
JeanMarcR Apr 30, 2021
7d1f5c4
STM32 TRNG : init update
JeanMarcR May 12, 2021
f599a54
STM32L5 RNG : update for deprecated MCU version
JeanMarcR May 12, 2021
b2b9c3d
README update STM32L5 to CUBE V1.4.0
JeanMarcR May 20, 2021
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2 changes: 1 addition & 1 deletion targets/TARGET_STM/README.md
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Expand Up @@ -73,7 +73,7 @@ This table summarizes the STM32Cube versions currently used in Mbed OS master br
| L0 | 1.12.0 | https://github.com/STMicroelectronics/STM32CubeL0 |
| L1 | 1.10.2 | https://github.com/STMicroelectronics/STM32CubeL1 |
| L4 | 1.17.0 | https://github.com/STMicroelectronics/STM32CubeL4 |
| L5 | 1.3.0 | https://github.com/STMicroelectronics/STM32CubeL5 |
| L5 | 1.4.0 | https://github.com/STMicroelectronics/STM32CubeL5 |
| WB | 1.11.1 | https://github.com/STMicroelectronics/STM32CubeWB |
| WL | 1.0.0 | https://github.com/STMicroelectronics/STM32CubeWL |

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25 changes: 19 additions & 6 deletions targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/CMSIS/stm32l552xx.h
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Expand Up @@ -164,8 +164,8 @@ typedef enum
HASH_IRQn = 96, /*!< HASH global interrupt */
LPTIM3_IRQn = 98, /*!< LPTIM3 global interrupt */
SPI3_IRQn = 99, /*!< SPI3 global interrupt */
I2C4_EV_IRQn = 100, /*!< I2C4 Event interrupt */
I2C4_ER_IRQn = 101, /*!< I2C4 Error interrupt */
I2C4_ER_IRQn = 100, /*!< I2C4 Error interrupt */
I2C4_EV_IRQn = 101, /*!< I2C4 Event interrupt */
DFSDM1_FLT0_IRQn = 102, /*!< DFSDM1 Filter 0 global interrupt */
DFSDM1_FLT1_IRQn = 103, /*!< DFSDM1 Filter 1 global interrupt */
DFSDM1_FLT2_IRQn = 104, /*!< DFSDM1 Filter 2 global interrupt */
Expand Down Expand Up @@ -1022,7 +1022,9 @@ typedef struct
__IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */
__IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */
__IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */
uint32_t RESERVED1[47];/*!< Reserved, Address offset: 0x54 -- 0xFC */
uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x44 -- 0x4C */
__IO uint32_t CFGR; /*!< TAMP configuration register, Address offset: 0x50 */
uint32_t RESERVED2[43];/*!< Reserved, Address offset: 0x54 -- 0xFC */
__IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
__IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
__IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
Expand Down Expand Up @@ -13974,9 +13976,20 @@ typedef struct
#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk

/******************** Bits definition for TAMP_COUNTR register ***************/
#define TAMP_COUNTR_Pos (16U)
#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */
#define TAMP_COUNTR TAMP_COUNTR_Msk
#define TAMP_COUNTR_Pos (16U)
#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */
#define TAMP_COUNTR TAMP_COUNTR_Msk

/******************** Bits definition for TAMP_CFGR register *****************/
#define TAMP_CFGR_TMONEN_Pos (1U)
#define TAMP_CFGR_TMONEN_Msk (0x1UL << TAMP_CFGR_TMONEN_Pos) /*!< 0x00000002 */
#define TAMP_CFGR_TMONEN TAMP_CFGR_TMONEN_Msk
#define TAMP_CFGR_VMONEN_Pos (2U)
#define TAMP_CFGR_VMONEN_Msk (0x1UL << TAMP_CFGR_VMONEN_Pos) /*!< 0x00000004 */
#define TAMP_CFGR_VMONEN TAMP_CFGR_VMONEN_Msk
#define TAMP_CFGR_WUTMONEN_Pos (3U)
#define TAMP_CFGR_WUTMONEN_Msk (0x1UL << TAMP_CFGR_WUTMONEN_Pos) /*!< 0x00000008 */
#define TAMP_CFGR_WUTMONEN TAMP_CFGR_WUTMONEN_Msk

/******************** Bits definition for TAMP_BKP0R register ***************/
#define TAMP_BKP0R_Pos (0U)
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25 changes: 19 additions & 6 deletions targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/CMSIS/stm32l562xx.h
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Expand Up @@ -166,8 +166,8 @@ typedef enum
PKA_IRQn = 97, /*!< PKA global interrupt */
LPTIM3_IRQn = 98, /*!< LPTIM3 global interrupt */
SPI3_IRQn = 99, /*!< SPI3 global interrupt */
I2C4_EV_IRQn = 100, /*!< I2C4 Event interrupt */
I2C4_ER_IRQn = 101, /*!< I2C4 Error interrupt */
I2C4_ER_IRQn = 100, /*!< I2C4 Error interrupt */
I2C4_EV_IRQn = 101, /*!< I2C4 Event interrupt */
DFSDM1_FLT0_IRQn = 102, /*!< DFSDM1 Filter 0 global interrupt */
DFSDM1_FLT1_IRQn = 103, /*!< DFSDM1 Filter 1 global interrupt */
DFSDM1_FLT2_IRQn = 104, /*!< DFSDM1 Filter 2 global interrupt */
Expand Down Expand Up @@ -1096,7 +1096,9 @@ typedef struct
__IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */
__IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */
__IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */
uint32_t RESERVED1[47];/*!< Reserved, Address offset: 0x54 -- 0xFC */
uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x44 -- 0x4C */
__IO uint32_t CFGR; /*!< TAMP configuration register, Address offset: 0x50 */
uint32_t RESERVED2[43];/*!< Reserved, Address offset: 0x54 -- 0xFC */
__IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
__IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
__IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
Expand Down Expand Up @@ -14713,9 +14715,20 @@ typedef struct
#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk

/******************** Bits definition for TAMP_COUNTR register ***************/
#define TAMP_COUNTR_Pos (16U)
#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */
#define TAMP_COUNTR TAMP_COUNTR_Msk
#define TAMP_COUNTR_Pos (16U)
#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */
#define TAMP_COUNTR TAMP_COUNTR_Msk

/******************** Bits definition for TAMP_CFGR register *****************/
#define TAMP_CFGR_TMONEN_Pos (1U)
#define TAMP_CFGR_TMONEN_Msk (0x1UL << TAMP_CFGR_TMONEN_Pos) /*!< 0x00000002 */
#define TAMP_CFGR_TMONEN TAMP_CFGR_TMONEN_Msk
#define TAMP_CFGR_VMONEN_Pos (2U)
#define TAMP_CFGR_VMONEN_Msk (0x1UL << TAMP_CFGR_VMONEN_Pos) /*!< 0x00000004 */
#define TAMP_CFGR_VMONEN TAMP_CFGR_VMONEN_Msk
#define TAMP_CFGR_WUTMONEN_Pos (3U)
#define TAMP_CFGR_WUTMONEN_Msk (0x1UL << TAMP_CFGR_WUTMONEN_Pos) /*!< 0x00000008 */
#define TAMP_CFGR_WUTMONEN TAMP_CFGR_WUTMONEN_Msk

/******************** Bits definition for TAMP_BKP0R register ***************/
#define TAMP_BKP0R_Pos (0U)
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2 changes: 1 addition & 1 deletion targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/CMSIS/stm32l5xx.h
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Expand Up @@ -79,7 +79,7 @@
*/
#define __STM32L5_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32L5_CMSIS_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */
#define __STM32L5_CMSIS_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
#define __STM32L5_CMSIS_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */
#define __STM32L5_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32L5_CMSIS_VERSION ((__STM32L5_CMSIS_VERSION_MAIN << 24U)\
|(__STM32L5_CMSIS_VERSION_SUB1 << 16U)\
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2 changes: 2 additions & 0 deletions targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/CMakeLists.txt
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Expand Up @@ -61,6 +61,7 @@ target_sources(mbed-stm32l5cube-fw
STM32L5xx_HAL_Driver/stm32l5xx_hal_smartcard.c
STM32L5xx_HAL_Driver/stm32l5xx_hal_smartcard_ex.c
STM32L5xx_HAL_Driver/stm32l5xx_hal_smbus.c
STM32L5xx_HAL_Driver/stm32l5xx_hal_smbus_ex.c
STM32L5xx_HAL_Driver/stm32l5xx_hal_spi.c
STM32L5xx_HAL_Driver/stm32l5xx_hal_spi_ex.c
STM32L5xx_HAL_Driver/stm32l5xx_hal_sram.c
Expand All @@ -82,6 +83,7 @@ target_sources(mbed-stm32l5cube-fw
STM32L5xx_HAL_Driver/stm32l5xx_ll_fmc.c
STM32L5xx_HAL_Driver/stm32l5xx_ll_gpio.c
STM32L5xx_HAL_Driver/stm32l5xx_ll_i2c.c
STM32L5xx_HAL_Driver/stm32l5xx_ll_icache.c
STM32L5xx_HAL_Driver/stm32l5xx_ll_lptim.c
STM32L5xx_HAL_Driver/stm32l5xx_ll_lpuart.c
STM32L5xx_HAL_Driver/stm32l5xx_ll_opamp.c
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