Skip to content

Commit 7d6d93f

Browse files
authored
machine: bump rp2040 to 200MHz (tinygo-org#4768)
* machine: add support for core voltage adjustments to rp2040 In preparation for bumping the core frequency of the rp2040, this change implements the required core voltage adjustment logic. * machine: bump rp2040 to 200MHz
1 parent 8c54e3d commit 7d6d93f

File tree

3 files changed

+30
-1
lines changed

3 files changed

+30
-1
lines changed

src/machine/machine_rp2_2040.go

+14-1
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ import (
99
)
1010

1111
const (
12-
cpuFreq = 125 * MHz
12+
cpuFreq = 200 * MHz
1313
_NUMBANK0_GPIOS = 30
1414
_NUMBANK0_IRQS = 4
1515
_NUMIRQ = 32
@@ -208,3 +208,16 @@ func (clks *clocksType) initTicks() {} // No ticks on RP2040
208208
func (wd *watchdogImpl) startTick(cycles uint32) {
209209
rp.WATCHDOG.TICK.Set(cycles | rp.WATCHDOG_TICK_ENABLE)
210210
}
211+
212+
func adjustCoreVoltage() bool {
213+
if cpuFreq <= 133*MHz {
214+
return false
215+
}
216+
// The rp2040 is certified to run at 200MHz with the
217+
// core voltage set to 1150mV.
218+
const targetVoltage = 1150
219+
// 0b0101 maps to 800mV and each step is 50mV.
220+
const vreg = 0b0101 + (targetVoltage-800)/50
221+
rp.VREG_AND_CHIP_RESET.SetVREG_VSEL(vreg)
222+
return true
223+
}

src/machine/machine_rp2_2350.go

+4
Original file line numberDiff line numberDiff line change
@@ -222,3 +222,7 @@ func EnterBootloader() {
222222
func (wd *watchdogImpl) startTick(cycles uint32) {
223223
rp.TICKS.WATCHDOG_CTRL.SetBits(1)
224224
}
225+
226+
func adjustCoreVoltage() bool {
227+
return false
228+
}

src/machine/machine_rp2_clocks.go

+12
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,10 @@ type clock struct {
4242
cix clockIndex
4343
}
4444

45+
// The delay in seconds for core voltage adjustments to
46+
// settle. Taken from the Pico SDK.
47+
const _VREG_VOLTAGE_AUTO_ADJUST_DELAY = 1 / 1e3
48+
4549
// clock returns the clock identified by cix.
4650
func (clks *clocksType) clock(cix clockIndex) clock {
4751
return clock{
@@ -188,6 +192,14 @@ func (clks *clocksType) init() {
188192
xoscFreq,
189193
xoscFreq)
190194

195+
if adjustCoreVoltage() {
196+
// Wait for the voltage to settle.
197+
const cycles = _VREG_VOLTAGE_AUTO_ADJUST_DELAY * xoscFreq * MHz
198+
for i := 0; i < cycles; i++ {
199+
arm.Asm("nop")
200+
}
201+
}
202+
191203
// clkSys = pllSys (125MHz) / 1 = 125MHz
192204
csys := clks.clock(clkSys)
193205
csys.configure(rp.CLOCKS_CLK_SYS_CTRL_SRC_CLKSRC_CLK_SYS_AUX,

0 commit comments

Comments
 (0)