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3 files changed +30
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lines changed Original file line number Diff line number Diff line change 9
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)
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const (
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- cpuFreq = 125 * MHz
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+ cpuFreq = 200 * MHz
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_NUMBANK0_GPIOS = 30
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_NUMBANK0_IRQS = 4
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_NUMIRQ = 32
@@ -208,3 +208,16 @@ func (clks *clocksType) initTicks() {} // No ticks on RP2040
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func (wd * watchdogImpl ) startTick (cycles uint32 ) {
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rp .WATCHDOG .TICK .Set (cycles | rp .WATCHDOG_TICK_ENABLE )
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}
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+
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+ func adjustCoreVoltage () bool {
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+ if cpuFreq <= 133 * MHz {
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+ return false
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+ }
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+ // The rp2040 is certified to run at 200MHz with the
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+ // core voltage set to 1150mV.
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+ const targetVoltage = 1150
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+ // 0b0101 maps to 800mV and each step is 50mV.
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+ const vreg = 0b0101 + (targetVoltage - 800 )/ 50
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+ rp .VREG_AND_CHIP_RESET .SetVREG_VSEL (vreg )
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+ return true
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+ }
Original file line number Diff line number Diff line change @@ -222,3 +222,7 @@ func EnterBootloader() {
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func (wd * watchdogImpl ) startTick (cycles uint32 ) {
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rp .TICKS .WATCHDOG_CTRL .SetBits (1 )
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}
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+
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+ func adjustCoreVoltage () bool {
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+ return false
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+ }
Original file line number Diff line number Diff line change @@ -42,6 +42,10 @@ type clock struct {
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cix clockIndex
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}
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+ // The delay in seconds for core voltage adjustments to
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+ // settle. Taken from the Pico SDK.
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+ const _VREG_VOLTAGE_AUTO_ADJUST_DELAY = 1 / 1e3
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+
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// clock returns the clock identified by cix.
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func (clks * clocksType ) clock (cix clockIndex ) clock {
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return clock {
@@ -188,6 +192,14 @@ func (clks *clocksType) init() {
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xoscFreq ,
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xoscFreq )
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+ if adjustCoreVoltage () {
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+ // Wait for the voltage to settle.
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+ const cycles = _VREG_VOLTAGE_AUTO_ADJUST_DELAY * xoscFreq * MHz
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+ for i := 0 ; i < cycles ; i ++ {
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+ arm .Asm ("nop" )
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+ }
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+ }
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+
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// clkSys = pllSys (125MHz) / 1 = 125MHz
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csys := clks .clock (clkSys )
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csys .configure (rp .CLOCKS_CLK_SYS_CTRL_SRC_CLKSRC_CLK_SYS_AUX ,
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