Committing TBB 2018 Update 5 source code

Author: tbbdev

CHANGES

@@ -2,6 +2,31 @@
 The list of most significant changes made over time in
 Intel(R) Threading Building Blocks (Intel(R) TBB).
 
+Intel TBB 2018 Update 5
+TBB_INTERFACE_VERSION == 10005
+
+Changes (w.r.t. Intel TBB 2018 Update 4):
+
+Preview Features:
+
+- Added user event tracing API for Intel(R) VTune(TM) Amplifier and
+    Flow Graph Analyzer.
+
+Bugs fixed:
+
+- Fixed the memory allocator to properly support transparent huge pages.
+- Removed dynamic exception specifications in tbbmalloc_proxy for C++11
+    and later (https://github.com/01org/tbb/issues/41).
+- Added -flifetime-dse=1 option when building with GCC on macOS*
+    (https://github.com/01org/tbb/issues/60).
+
+Open-source contributions integrated:
+
+- Added ARMv8 support by Siddhesh Poyarekar.
+- Avoid GCC warnings for clearing an object of non-trivial type
+    (https://github.com/01org/tbb/issues/54) by Daniel Arndt.
+
+------------------------------------------------------------------------
 Intel TBB 2018 Update 4
 TBB_INTERFACE_VERSION == 10004
 

README.md

@@ -1,5 +1,5 @@
-# Intel(R) Threading Building Blocks 2018 Update 4
-[![Stable release](https://img.shields.io/badge/version-2018_U4-green.svg)](https://github.com/01org/tbb/releases/tag/2018_U4)
+# Intel(R) Threading Building Blocks 2018 Update 5
+[![Stable release](https://img.shields.io/badge/version-2018_U5-green.svg)](https://github.com/01org/tbb/releases/tag/2018_U5)
 [![Apache License Version 2.0](https://img.shields.io/badge/license-Apache_2.0-green.svg)](LICENSE)
 
 Intel(R) Threading Building Blocks (Intel(R) TBB) lets you easily write parallel C++ programs that take
@@ -8,6 +8,8 @@ full advantage of multicore performance, that are portable, composable and have
 ## Release Information
 Here are the latest [Changes](CHANGES) and [Release Notes](doc/Release_Notes.txt) (contains system requirements and known issues).
 
+Since [2018 U5](https://github.com/01org/tbb/releases/tag/2018_U5) TBB binary packages include [Parallel STL](https://github.com/intel/parallelstl) as a high-level component.
+
 ## Documentation
 * Intel(R) TBB [tutorial](https://software.intel.com/en-us/tbb-tutorial)
 * Intel(R) TBB general documentation: [stable](https://software.intel.com/en-us/tbb-documentation)

build/Makefile.tbbmalloc

@@ -175,6 +175,12 @@ $(MALLOC_ADD_DLL_TESTS): %.$(TEST_EXT): %_dll.$(DLL)
 $(MALLOC_ADD_DLL_TESTS): TEST_LIBS+=$(@:.$(TEST_EXT)=_dll.$(LIBEXT))
 endif
 
+# test_malloc_pure_c is intended to be compiled by CONLY
+# compiler. Hence cannot include any C++-compiler options.
+# TODO: separate C and C++ compiler options (i.e. C_FLAGS and CPLUS_FLAGS).
+test_malloc_pure_c.$(TEST_EXT): CPLUS_FLAGS := $(subst -Woverloaded-virtual,,$(CPLUS_FLAGS))
+test_malloc_pure_c.$(TEST_EXT): CPLUS_FLAGS := $(subst -Wnon-virtual-dtor,,$(CPLUS_FLAGS))
+
 test_malloc_over%.$(TEST_EXT): CPLUS_FLAGS=$(subst /MT,/MD,$(M_CPLUS_FLAGS))
 test_malloc_over%.$(TEST_EXT): INCLUDES=$(M_INCLUDES)
 test_malloc_overload_proxy.$(TEST_EXT): LINK_FLAGS+=$(LIBDL)

build/macos.gcc.inc

@@ -38,6 +38,24 @@ LINK_FLAGS =
 LIB_LINK_FLAGS = -dynamiclib -install_name @rpath/$(BUILDING_LIBRARY)
 C_FLAGS = $(CPLUS_FLAGS)
 
+# gcc 4.8 and later support RTM intrinsics, but require command line switch to enable them
+ifneq (,$(shell gcc -dumpversion | egrep  "^(4\.[8-9]|[5-9])"))
+    RTM_KEY = -mrtm
+endif
+
+# gcc 5.0 and later have -Wsuggest-override option
+# enable it via a pre-included header in order to limit to C++11 and above
+ifneq (,$(shell gcc -dumpversion | egrep  "^([5-9])"))
+    INCLUDE_TEST_HEADERS = -include $(tbb_root)/src/test/harness_preload.h
+endif
+
+# gcc 6.0 and later have -flifetime-dse option that controls
+# elimination of stores done outside the object lifetime
+ifneq (,$(shell gcc -dumpversion | egrep  "^([6-9])"))
+    # keep pre-contruction stores for zero initialization
+    DSE_KEY = -flifetime-dse=1
+endif
+
 ifeq ($(cfg), release)
     CPLUS_FLAGS = -g -O2
 else