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| 1 | +# Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. |
| 2 | +# |
| 3 | +# Redistribution and use in source and binary forms, with or without |
| 4 | +# modification, are permitted provided that the following conditions # are met: |
| 5 | +# * Redistributions of source code must retain the above copyright |
| 6 | +# notice, this list of conditions and the following disclaimer. |
| 7 | +# * Redistributions in binary form must reproduce the above copyright |
| 8 | +# notice, this list of conditions and the following disclaimer in the |
| 9 | +# documentation and/or other materials provided with the distribution. |
| 10 | +# * Neither the name of NVIDIA CORPORATION nor the names of its |
| 11 | +# contributors may be used to endorse or promote products derived |
| 12 | +# from this software without specific prior written permission. |
| 13 | +# |
| 14 | +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY |
| 15 | +# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 16 | +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 17 | +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 18 | +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 19 | +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 20 | +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
| 21 | +# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY |
| 22 | +# OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 23 | +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 24 | +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 25 | + |
| 26 | +name: "single_state_buffer" |
| 27 | +backend: "implicit_state" |
| 28 | +max_batch_size: 0 |
| 29 | +sequence_batching { |
| 30 | + control_input [ |
| 31 | + { |
| 32 | + name: "START" |
| 33 | + control [ |
| 34 | + { |
| 35 | + kind: CONTROL_SEQUENCE_START |
| 36 | + fp32_false_true: [ 0, 1 ] |
| 37 | + } |
| 38 | + ] |
| 39 | + }, |
| 40 | + { |
| 41 | + name: "READY" |
| 42 | + control [ |
| 43 | + { |
| 44 | + kind: CONTROL_SEQUENCE_READY |
| 45 | + fp32_false_true: [ 0, 1 ] |
| 46 | + } |
| 47 | + ] |
| 48 | + }, |
| 49 | + { |
| 50 | + name: "END" |
| 51 | + control [ |
| 52 | + { |
| 53 | + kind: CONTROL_SEQUENCE_END |
| 54 | + fp32_false_true: [ 0, 1 ] |
| 55 | + } |
| 56 | + ] |
| 57 | + } |
| 58 | + ] |
| 59 | + state [ |
| 60 | + { |
| 61 | + input_name: "INPUT_STATE" |
| 62 | + output_name: "OUTPUT_STATE" |
| 63 | + data_type: TYPE_INT32 |
| 64 | + dims: 1 |
| 65 | + use_single_buffer: true |
| 66 | + } |
| 67 | + ] |
| 68 | +} |
| 69 | + |
| 70 | +input [ |
| 71 | + { |
| 72 | + name: "INPUT" |
| 73 | + data_type: TYPE_INT32 |
| 74 | + dims: [ 1 ] |
| 75 | + }, |
| 76 | + { |
| 77 | + name: "TEST_CASE" |
| 78 | + data_type: TYPE_INT32 |
| 79 | + dims: [ 1 ] |
| 80 | + } |
| 81 | +] |
| 82 | + |
| 83 | +output [ |
| 84 | + { |
| 85 | + name: "OUTPUT" |
| 86 | + data_type: TYPE_INT32 |
| 87 | + dims: [ 1 ] |
| 88 | + } |
| 89 | +] |
| 90 | + |
| 91 | +instance_group [ |
| 92 | + { |
| 93 | + count: 1 |
| 94 | + kind : KIND_CPU |
| 95 | + } |
| 96 | +] |
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