targets/pipistrello: Enable SPI flash.

Author: mithro

platforms/opsis.py

@@ -357,9 +357,27 @@ class Platform(XilinxPlatform):
     default_clk_period = 10.0
     hdmi_infos = _hdmi_infos
 
+    # W25Q128FVEIG - component U3
+    # 128M (16M x 8) - 104MHz
+    # Pretends to be a Micron N25Q128 (ID 0x0018ba20)
+    # FIXME: Create a "spi flash module" object in the same way we have SDRAM
+    # module objects.
+    spiflash_read_dummy_bits = 10
+    spiflash_clock_div = 4
+    spiflash_total_size = int((128/8)*1024*1024) # 128Mbit
+    spiflash_page_size = 256
+    spiflash_sector_size = 0x10000
+
+
+    # The Opsis has a XC6SLX45 which bitstream takes up ~12Mbit (1484472 bytes)
+    # 0x200000 offset (16Mbit) gives plenty of space
+    gateware_size = 0x200000
+
+
     def __init__(self, programmer="openocd"):
         # XC6SLX45T-3FGG484C
         XilinxPlatform.__init__(self,  "xc6slx45t-fgg484-3", _io, _connectors)
+        self.programmer = programmer
 
         pins = {
           'ProgPin': 'PullUp',
@@ -373,15 +391,14 @@ def __init__(self, programmer="openocd"):
         for pin, config in pins.items():
             self.toolchain.bitgen_opt += " -g %s:%s " % (pin, config)
 
-        self.programmer = programmer
-
         # FPGA AUX is connected to the 3.3V supply
         self.add_platform_command("""CONFIG VCCAUX="3.3";""")
 
     def create_programmer(self):
 	# Preferred programmer - Needs ixo-usb-jtag and latest openocd.
+        proxy="bscan_spi_{}.bit".format(self.device.split('-')[0])
         if self.programmer == "openocd":
-            return OpenOCD(config="board/numato_opsis.cfg")
+            return OpenOCD(config="board/numato_opsis.cfg", flash_proxy_basename=proxy)
 	# Alternative programmers - not regularly tested.
         elif self.programmer == "urjtag":
             return UrJTAG(cable="USBBlaster")

targets/opsis_base.py

@@ -9,6 +9,7 @@
 from migen.genlib.record import Record
 
 from misoclib.com import gpio
+from misoclib.mem.flash import spiflash
 from misoclib.mem.sdram.module import MT41J128M16
 from misoclib.mem.sdram.phy import s6ddrphy
 from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
@@ -135,6 +136,7 @@ class BaseSoC(SDRAMSoC):
     default_platform = "opsis"
 
     csr_peripherals = (
+        "spiflash",
         "ddrphy",
         "dna",
         "git_info",
@@ -148,6 +150,7 @@ class BaseSoC(SDRAMSoC):
 
     mem_map = {
         "firmware_ram": 0x20000000,  # (default shadow @0xa0000000)
+        "spiflash":     0x30000000,  # (default shadow @0xb0000000)
     }
     mem_map.update(SDRAMSoC.mem_map)
 
@@ -203,6 +206,13 @@ def __init__(self, platform,
             ]
             self.register_sdram_phy(self.ddrphy)
 
+        self.submodules.spiflash = spiflash.SpiFlash(
+            platform.request("spiflash4x"), dummy=platform.spiflash_read_dummy_bits, div=platform.spiflash_clock_div)
+        self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
+        self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size)
+        self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size
+        self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=platform.gateware_size)
+
         self.specials += Keep(self.crg.cd_sys.clk)
         platform.add_platform_command("""
 NET "{sys_clk}" TNM_NET = "GRPsys_clk";
@@ -222,7 +232,7 @@ class MiniSoC(BaseSoC):
     interrupt_map.update(BaseSoC.interrupt_map)
 
     mem_map = {
-        "ethmac": 0x30000000,  # (shadow @0xb0000000)
+        "ethmac": 0x40000000,  # (shadow @0xc0000000)
     }
     mem_map.update(BaseSoC.mem_map)
 

targets/pipistrello_base.py

@@ -1,21 +1,22 @@
+# Support for the Pipistrello - http://pipistrello.saanlima.com/
 from fractions import Fraction
-import struct
 
 from migen.fhdl.std import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 from migen.bus import wishbone
 
 from misoclib.com import gpio
+from misoclib.mem.flash import spiflash
 from misoclib.mem.sdram.module import MT46H32M16
 from misoclib.mem.sdram.phy import s6ddrphy
 from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
-from misoclib.mem.flash import spiflash
 from misoclib.soc.sdram import SDRAMSoC
 
 from gateware import dna
 from gateware import firmware
 from gateware import git_info
 from gateware import hdmi_out
+from gateware import i2c
 from gateware import i2c_hack
 from gateware import platform_info
 
@@ -133,16 +134,18 @@ class BaseSoC(SDRAMSoC):
 
     mem_map = {
         "firmware_ram": 0x20000000,  # (default shadow @0xa0000000)
+        "spiflash": 0x30000000,  # (default shadow @0xb0000000)
     }
     mem_map.update(SDRAMSoC.mem_map)
 
-    def __init__(self, platform, clk_freq=(83 + Fraction(1, 3))*1000*1000,
-                 sdram_controller_settings=LASMIconSettings(l2_size=32,
-                                                            with_bandwidth=True),
-                 firmware_ram_size=0xa000, firmware_filename=None, **kwargs):
+    def __init__(self, platform,
+                 firmware_ram_size=0xa000,
+                 firmware_filename=None,
+                 **kwargs):
+        clk_freq = (83 + Fraction(1, 3))*1000*1000
         SDRAMSoC.__init__(self, platform, clk_freq,
                           integrated_rom_size=0x8000,
-                          sdram_controller_settings=sdram_controller_settings,
+                          sdram_controller_settings=LASMIconSettings(l2_size=32, with_bandwidth=True),
                           **kwargs)
 
         platform.add_extension(PipistrelloCustom)
@@ -169,19 +172,12 @@ def __init__(self, platform, clk_freq=(83 + Fraction(1, 3))*1000*1000,
             ]
             self.register_sdram_phy(self.ddrphy)
 
-        if not self.integrated_rom_size:
-            self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"),
-                                                         dummy=10, div=4)
-            self.add_constant("SPIFLASH_PAGE_SIZE", 256)
-            self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
-            self.flash_boot_address = 0x180000
-            self.register_rom(self.spiflash.bus, 0x1000000)
-        platform.add_platform_command("""PIN "hdmi_out_pix_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;""")
-
-_hdmi_infos = {
-    "HDMI_OUT0_MNEMONIC": "J4",
-    "HDMI_OUT0_DESCRIPTION": "XXX",
-}
+        self.submodules.spiflash = spiflash.SpiFlash(
+            platform.request("spiflash4x"), dummy=platform.spiflash_read_dummy_bits, div=platform.spiflash_clock_div)
+        self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
+        self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size)
+        self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size
+        self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=platform.gateware_size)
 
 
 class VideomixerSoC(BaseSoC):
@@ -196,7 +192,9 @@ def __init__(self, platform, **kwargs):
         self.submodules.hdmi_out0 = hdmi_out.HDMIOut(
             platform.request("hdmi", 0), self.sdram.crossbar.get_master())
 
-        for k, v in _hdmi_infos.items():
+        platform.add_platform_command("""PIN "hdmi_out_pix_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;""")
+
+        for k, v in platform.hdmi_infos.items():
             self.add_constant(k, v)
 
 default_subtarget = VideomixerSoC