Updating submodules.

 * litedram changed from 5b02791 to f36bcff
    * f36bcff - phy/gensdrphy: cleanup/simplify pass <Florent Kermarrec>
    * da06715 - core/bankmachine: typo <Florent Kermarrec>
    * ab0d519 - core: change cba_shift parameter to more explicit address_mapping parameter <Florent Kermarrec>
    * 230ea24 - core: simplify/cleanup pass <Florent Kermarrec>
    * 94b844d - core/frontend: move crossbar to core <Florent Kermarrec>
    * 8d24163 - phy/s7ddrphy: use our own bitslip module in fabric <Florent Kermarrec>
    * 20d7675 - phy/s7ddrphy: add additional_read_latency parameter <Florent Kermarrec>
    * f11506a - examples/litedram_gen: cleanup pins definition <Florent Kermarrec>
    * 75b314c - modules: update K4B2G1646F and use timings from datasheet <Florent Kermarrec>
    * b71ed35 - core/bankmachine: manage tRC <Florent Kermarrec>
    * 0abb3e4 - modules: use tRAS and tRP to compute tRC (tRC = tRAS + tRP) <Florent Kermarrec>
    * 9a950f0 - ecc: update core/test <Florent Kermarrec>
    * 8a0d0f0 - phy/s7ddrphy: remove hacky bl8 variant (see #60) <Florent Kermarrec>
    * 5fe4868 - modules: add trrd to all ddr3 modules <Florent Kermarrec>
    *   dbfa929 - Merge pull request #59 from enjoy-digital/tRRD_Fix <enjoy-digital>
    |\
    | * 5315d27 - tRRD incorrectly specified <[email protected]>
    |/
    * 167c0c9 - remove partial reordering code in master, keep things in bank_reordering branch. <Florent Kermarrec>
    * 828129e - core/bank_machine: simplify trascon <Florent Kermarrec>
    * 4fa64c8 - core/bankmachine: remove trccon (activate_allowed not used) <Florent Kermarrec>
    * feac98f - core/bankmachine: use tXXDController everywhere (better timings) <John Sully>
    * bce411e - common: move tXXDController to common <John Sully>
    * fef4701 - core/multiplexer: select all ranks on refresh <Florent Kermarrec>
    * 3481d45 - core/multiplexer: fix rank_decoder width <Florent Kermarrec>
    * 3b5a1ff - modules: add K4B1G0446F <Florent Kermarrec>
    * 48c17ce - modules: fix tWTR regression on MT46H32M32 <Florent Kermarrec>
    * ad0a1d4 - modules: improve timings definition (keep retro-compatibility with previous definitions) <Florent Kermarrec>

 * litepcie changed from a09d225 to a8b8048
    * a8b8048 - core/tlp/reordering: increase buffering <Florent Kermarrec>
    * 9578a3c - LICENSE: typo <Florent Kermarrec>
    * b37065c - Merge pull request #13 from enjoy-digital/reordering <enjoy-digital>
    * 62d6217 - core/tlp/reordering: use buffered=True <Florent Kermarrec>
    * 35a4aa8 - core/tlp/reordering: use buffered data fifo to ease timings <Florent Kermarrec>
    * 288c5f9 - core/tlp/reordering: refactor/simplify <Florent Kermarrec>
    * 1f39ee2 - core/tlp/controller: use log2_int everywhere <Florent Kermarrec>

 * litex changed from 6e327cda to 3e189379
    * 3e189379 - boards/targets: add versa ecp55g prjtrellis target (experimental) <Florent Kermarrec>
    * a69197d2 - build/lattice: add initial prjtrellis support <Florent Kermarrec>
    * 397e3c76 - build/lattice/diamond: use bash on linux <Florent Kermarrec>
    * d029cd24 - build/lattice: improve special_overrides names (vendor_family) <Florent Kermarrec>
    *   60665358 - Merge pull request #114 from mithro/xilinx+yosys <enjoy-digital>
    |\
    | *   b200ce99 - Merge branch 'master' into xilinx+yosys <enjoy-digital>
    | |\
    | |/
    |/|
    * |   8c0982a1 - Merge pull request #118 from mithro/uart-sync <enjoy-digital>
    |\ \
    | * | ba0dd572 - uart: Enable buffering the FIFO. <Tim 'mithro' Ansell>
    |/ /
    * | f9167053 - README: improve instructions for litex_sim <Florent Kermarrec>
    * | e3935b48 - build/sim/verilator: don't use THEADS parameters when threads=1 <Florent Kermarrec>
    * | a44181e7 - soc_sdram: update litedram <Florent Kermarrec>
    * | ab6a530a - bios/sdram: s7ddrphy now has bitslip in fabric, show scan for each module/bitslip and remove silent mode <Florent Kermarrec>
    * | b8be9545 - build/xilinx/vivado: enable xpm libraries <Florent Kermarrec>
    * | ab8cf3e3 - soc/cores/clock: add margin parameter to create_clkout (default = 1%) <Florent Kermarrec>
    * | 915c2f41 - bios/sdram: improve write/read leveling <Florent Kermarrec>
    * | deffa603 - platforms/kc705: add ddram_dual_rank <Florent Kermarrec>
    * | 10624c26 - bios/main: handle all types of carriage return (\r, \n, \r\n or \n\r) <Florent Kermarrec>
    * |   9f083e9b - Merge pull request #116 from stffrdhrn/sim-uart <enjoy-digital>
    |\ \
    | * | 8877dba7 - sim: serial: Send '\r\n' instead of just '\n' <Stafford Horne>
    |  /
    * | d1879215 - cpu_interface: fix select_triple when only one specified <Florent Kermarrec>
    * | 3b27d2ae - soc/integration/cpu_interface: generate error if unable to find any of the cross compilation toolchains <Florent Kermarrec>
    * | 168b07b9 - soc_core: add csr range check <Florent Kermarrec>
    * |   6febb682 - Merge pull request #112 from cr1901/8k-b-evn <enjoy-digital>
    |\ \
    | * | 9a44f08a - build/platforms: Add ice40_hx8k_b_evn from Migen. <William D. Jones>
    |  /
    * |   9cf4ffb3 - Merge pull request #113 from stffrdhrn/litex-trivial <enjoy-digital>
    |\ \
    | * | ff6de429 - Fix help for or1k builds <Stafford Horne>
    | * | dafdb8df - Fix compiler warnings from GCC 8.1 <Stafford Horne>
    |/ /
    * | 2be52054 - build/xilinx/common: update XilinxDDRInputImplS7 and XilinxDDRInputImplKU (from migen) <Florent Kermarrec>
    | * ace97624 - build.xilinx: Convert attributes to something Yosys understands. <Tim 'mithro' Ansell>
    | * 78414c05 - xilinx/viviado: Allow yosys for synthesis. <Tim 'mithro' Ansell>
    | * d13ac3b3 - cpu/mor1kx: Adding verilog include directory. <Tim 'mithro' Ansell>
    | * dc7cd757 - build.xilinx: Run `phys_opt_design` and generate timing report. <Tim 'mithro' Ansell>
    |/
    * 948527b0 - cores/cpu: revert vexriscv (it seems there is a regression in last version) <Florent Kermarrec>
    * 15bca453 - targets/sim: fix integrated_main_ram_size when with_sdram <Florent Kermarrec>

 * migen changed from 0.6.dev-173-gd3b875b to 0.6.dev-179-g657c0c7
    * 657c0c7 - class TSTriple: width is the width of the base signal <Staf Verhaegen>
    * 2d62c0c - platforms/ice40_up5k_b_evn: Add I/O connector and some default I/O (including spiflash). <William D. Jones>
    * ea6e483 - Fix issue where BusSynchronizer fails when iclock << oclock <bunnie>
    * 076ec0d - fhdl.visit: fix nondeterminism in visit_Case. <whitequark>
    * 1e114c7 - add a print to show user context when an exception is raised while evaluating a generator yield statement in simulation <N. Engelhardt>
    * ba63364 - platforms/ice40_hx8k_b_evn: Add pins for spiflash io. <William D. Jones>

Full submodule status
--
 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 f36bcff49fe96867503c219dd705ff8d7eb951cd litedram (remotes/origin/HEAD)
 40b99ecc05ee490d77477cba542db6d63333c390 liteeth (remotes/origin/HEAD)
 a8b804809d84e2125eb603bf9feefc9cef31d22b litepcie (remotes/origin/HEAD)
 b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD)
 1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD)
 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD)
 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD)
 3e189379f9272ba184fcdcfe077eb139f1f0fc7f litex (heads/master)
 657c0c72e63597162837809dfe3635d69a98cfd9 migen (0.6.dev-179-g657c0c7)

Author: cr1901