Updating submodules.

 * edid-decode changed from 15df4ae to 42f5fa4
    * 42f5fa4 - edid-decode: add comment w.r.t. JOC <Hans Verkuil>
    * a479a24 - edid-decode: parse additional flags in the DD+ Short Audio Descriptor <Arnaud Vrac>

 * litedram changed from 67de3ce to 6c53996
    * 6c53996 - core/refresher: reduce refresh period by one cycle <Florent Kermarrec>
    * afb6d0a - core/refresher: reduce RefreshGenerator start delay by 1 cycle <Florent Kermarrec>
    * b543286 - test/test_refresh: add Refresher test <Florent Kermarrec>
    * 7daf355 - test/test_bist: remove vcd generation (only useful for debug) <Florent Kermarrec>
    * b4125fa - test/test_refresh: add RefreshTimer test <Florent Kermarrec>
    * 9584c2f - test: remove use of rand_wait, rename rand_level to random <Florent Kermarrec>
    * 0eef5d4 - test: add test_refresh with simple RefreshGenerator test <Florent Kermarrec>
    * 9348800 - test: rename test_timing_controllers to test_timing <Florent Kermarrec>
    * 8cf561d - test/test_timing_controllers: add simple tFAWController tests <Florent Kermarrec>
    * 3ae666d - test/test_timing_controllers: add simple tXXDController tests <Florent Kermarrec>
    * 394a49a - test: add test_timing_controllers with tXXDController test <Florent Kermarrec>
    * 6e3f769 - core: move timing controllers to common <Florent Kermarrec>
    * 54cdc7f - test: -x on tests <Florent Kermarrec>
    * 2ecb053 - frontend/ecc: move generic part of ECC to LiteX <Florent Kermarrec>
    * 8646b2e - test/test_adaption: use same DUT for up/down converter tests <Florent Kermarrec>
    * 9f9fed0 - test: merge test_downconverter/test_upconverter in a single test_adaptation file <Florent Kermarrec>
    * fc41751 - frontend/dma: simplify rsv_level expose <Florent Kermarrec>
    *   88835de - Merge pull request #86 from sergachev/master <enjoy-digital>
    |\
    | * f145287 - dma: expose reservation level in the reader <Ilia Sergachev>
    |/
    * f018c9e - add CONTRIBUTORS file and add copyright header to all files. <Florent Kermarrec>
    * 18dda2d - phy/s7ddrphy: increase _half_sys8x_taps CSR to 5 bits <Florent Kermarrec>
    * 690e4f8 - README: fix ECP5 frequency ratio <Florent Kermarrec>

 * liteeth changed from 2424e62 to ad187d3
    * ad187d3 - add CONTRIBUTORS file and add copyright header to all files <Florent Kermarrec>
    * fd6d6c3 - mac: update imports <Florent Kermarrec>
    * a170acd - change MAC location (next to phy/core/frontend), keep import retro-compatibility <Florent Kermarrec>
    * 789dadd - liteeth/software: remove libwip/libuip examples. <Florent Kermarrec>

 * litepcie changed from de6cd01 to 71c9a3a
    * 71c9a3a - core/tlp: rewrite controller (simplify, always enable reordering) <Florent Kermarrec>
    * 619f5c5 - add CONTRIBUTORS file and copyright header to all files. <Florent Kermarrec>

 * litesata changed from 6fe4cce to db5d2f7
    * db5d2f7 - add CONTRIBUTORS and copyright header to all files. <Florent Kermarrec>

 * litescope changed from 2474ce9 to 9e3b9d8
    * 9e3b9d8 - add CONTRIBUTORS file and add copyright header to all files. <Florent Kermarrec>
    * 66956cb - Merge pull request #13 from keesj/arty_fast_scope <enjoy-digital>
    * 144bd06 - Add an example of sampling at 800Mhz using a serdes on arty. <kees.jongenburger>
    * 7f4dc39 - Add functionality to flatten values that are sampled using a serdes. <kees.jongenburger>

 * liteusb changed from 0a9110f to 7457a29
    * 7457a29 - README: deprecate, indicate new code location <Florent Kermarrec>

 * litex changed from 113f7f40 to e637aa65
    *   e637aa65 - Merge pull request #222 from antmicro/bump_vexriscv <enjoy-digital>
    |\
    | * 932475a2 - cpu/vexriscv: bump submodule <Mateusz Holenko>
    |/
    * bc7ab637 - bios/sdram: fix compilation warning <Florent Kermarrec>
    * a7895e49 - test/test_axi: remove use of rand_wait, rename rand_level to random <Florent Kermarrec>
    * 1cfb36e1 - soc_core: round memory regions size/length to next power of 2 (if not already a power of 2) <Florent Kermarrec>
    *   556d2c7c - Merge pull request #221 from antmicro/bump_vexriscv <enjoy-digital>
    |\
    | * 3e89c564 - cpu/vexriscv: bump submodule <Mateusz Holenko>
    |/
    * e673fce4 - bios/boot: fix default EMULATOR_RAM_BASE <Florent Kermarrec>
    * 0acacbaa - cores/clock: cleanup <Florent Kermarrec>
    * edf8aa8c - cores/clock: add initial iCE40 support <Florent Kermarrec>
    * 6d543358 - cores/spi_flash/add_clk_primitive: return if clk primitive is not needed <Florent Kermarrec>
    * 462d12ba - bios/boot: define EMULATOR_RAM_BASE if not defined, add KERNEL_IMAGE_RAM_OFFSET <Florent Kermarrec>
    * fc12961e - soc_core: fix cpu_variant definition <Florent Kermarrec>
    * af61688d - bios/boot: fix booting rework <Florent Kermarrec>
    * 4b686dbd - soc_core: fix cpu_variant config (we don't want the extension) <Florent Kermarrec>
    *   7d9cf1d2 - Merge pull request #216 from antmicro/booting_vexriscv_linux <enjoy-digital>
    |\
    | * 8335f13f - bios/boot: rework netboot/flashboot for VexRiscv in linux variant <Mateusz Holenko>
    | * a19bdd0e - soc_core: generate extra string-based config defines <Mateusz Holenko>
    | * 005c0776 - soc_core: include information about cpu variant in csv and headers <Mateusz Holenko>
    * | 95cfd0b9 - cores/spi_flash: add SpiFlashCommon and use it to add clk primitives (7-Series/ECP5 support for now) <Florent Kermarrec>
    * | bfdcf4b2 - platforms/versa_ecp5: add spiflash pads <Florent Kermarrec>
    * | 41eb21b3 - soc_core: optimize mem_decoder <Florent Kermarrec>
    * | 0eff65bb - cores/up5ksram: optimize bus.adr decoding <Florent Kermarrec>
    * | bb99c468 - cores/up5kspram: simplify and add support for all width/depth configurations <Florent Kermarrec>
    * | eaf84b85 - cores/pwm: remove clock_domain support (better to use ClockDomainsRenamer), make csr optional <Florent Kermarrec>
    * | ea619e3a - cores/spi: rename add_control paramter to add_csr <Florent Kermarrec>
    * | ec411a6a - soc_core: add SoCMini class (SoCCore with no cpu, sram, uart, timer) for simple designs <Florent Kermarrec>
    * |   bca42f74 - Merge pull request #219 from flammit/fix-ecp5-pll <enjoy-digital>
    |\ \
    | |/
    |/|
    | * c6c74391 - soc: cores: fix name of EHXPLLL output clock in ECP5PLL <Francis Lam>
    |/
    * d3aaaf5e - cores/spi: fix/simplify loopback <Florent Kermarrec>
    * 59fda8da - README: update banner <Florent Kermarrec>
    * 769d15d4 - cores/spi: move CSR control/status to add_control method, add loopback capability and simple xfer loopback test <Florent Kermarrec>
    * ee8fec10 - soc/cores: add ECC (Error Correcting Code) <Florent Kermarrec>
    * 7dbddb3a - platforms/tinyfpga_bx: add serial extension <Florent Kermarrec>
    * 831a1916 - README: add a few links to papers/presentations/tutorials <Florent Kermarrec>
    *   95796c5b - Merge pull request #218 from railnova/zynq <enjoy-digital>
    |\
    | * dcf55ad4 - [fix] Slave interface HP0 clk name <chmousset>
    * |   08772fc0 - Merge pull request #217 from sergachev/master <enjoy-digital>
    |\ \
    | |/
    |/|
    | * dacec6aa - spi: change CSR to CSRStorage <Ilia Sergachev>
    |/
    * be280bed - soc_zynq: use zynq fabric reset as sys reset <Florent Kermarrec>
    * 220f4375 - soc_zynq: add missing axi hp0 clock <Florent Kermarrec>
    * 9c8c0371 - soc_zynq: move axi gp0 clock connection to add_gp0 method <Florent Kermarrec>
    * b0192e5f - soc_core: use fixed 16MB CSR address space <Florent Kermarrec>
    * 68a50317 - soc_sdram: limit main_ram to 512MB for now <Florent Kermarrec>
    * ccbf1418 - compiler-rt: update to new location, fixes #209 <Florent Kermarrec>
    * 21a5aaa4 - soc_core: declare csr address size when registering csr, fixes #212 <Florent Kermarrec>
    * 41b6fbde - soc_cores: fix typos <Florent Kermarrec>
    *   bff081a8 - Merge pull request #214 from gsomlo/gls-alignment-fixup <enjoy-digital>
    |\
    | * e42f33ed - soc_core: additional csr_alignment follow-up fixes <Gabriel L. Somlo>
    |/
    * f4770219 - soc_core: add csr_alignment to allow 64-bit alignment with 64-bit CPUs <Florent Kermarrec>
    * 927b7c13 - soc/integration: uniformize configuration constants declaration in SoCs (use self.config instead self.add_constant) <Florent Kermarrec>
    * 96f45bbd - software/libbase/id: update code (length is now fixed to 256) <Florent Kermarrec>
    * 282ae963 - cores: add simple PWM (Pulse Width Modulation) module <Florent Kermarrec>
    * 77e7f9b3 - core/spi: make cs_n optional (sometimes managed externally) <Florent Kermarrec>
    * e726ad80 - cores/spi_flash: add non-memory mapped S7SPIFlash modules based on SPIMaster (for design were we only want to re-program the bistream) <Florent Kermarrec>
    * 4c18c991 - cores: add ICAP core (tested with reconfiguration commands) <Florent Kermarrec>
    * 6b82f23c - cores: add simple and minimal hardware SPI Master with CPOL=0, CPHA=0 and build time configurable data_width and frequency. <Florent Kermarrec>
    * ada70e8c - soc/cores/spi: remove too complicated and does not seem reliable in all cases. <Florent Kermarrec>
    * 7cd5c0f3 - cores: add bitbang class with minimal hardware for I2C/SPI software bit-banging <Florent Kermarrec>
    * d29b8419 - cores: remove nor_flash_16 (obsolete, most of the boards are now using SPI flash) <Florent Kermarrec>
    * 3f6bd266 - cores/gpio: remove Blinker <Florent Kermarrec>
    *   359b8fe4 - Merge pull request #210 from DurandA/master <Tim Ansell>
    |\
    | * 68eeba91 - Add verilog submodule from CPU cores to manifest <Arnaud Durand>
    |/
    * 4ee9c53f - csr: add assert to ensure CSR size < busword (thanks tweakoz) <Florent Kermarrec>
    * 0116b2b7 - soc_core: update default RocketChip mem_map <Florent Kermarrec>
    * 9d170b09 - soc_core: rearrange default mem_map <Florent Kermarrec>
    * 05b667bb - bios/main: fix #ifdefs for fw command <Florent Kermarrec>
    * 37687579 - libnet/tftp: fix compilation warning <Florent Kermarrec>
    * 9f3c8a9b - bios/main: fix spiflash compilation warnings <Florent Kermarrec>
    * 2da59b29 - soc_sdram: allow main_ram_size > 256MB (limitation no longer exists) <Florent Kermarrec>
    * b8d45af5 - targets: use new prefered way to add wishbone slave <Florent Kermarrec>
    * 7618b845 - soc_core: use new way to add wisbone slave (now prefered) <Florent Kermarrec>
    * 740629ba - soc_core: remove 256MB mem_map limitation <Florent Kermarrec>
    * b65968c3 - soc/core: remove #!/usr/bin/env python3 <Florent Kermarrec>
    *   f49d0fe6 - Merge pull request #206 from gsomlo/gls-tftp-spinner <enjoy-digital>
    |\
    | * 5a42dbf3 - BIOS: TFTP: ASCII spinner progress indicator (cosmetic) <Gabriel L. Somlo>
    |/
    *   d5177d72 - Merge pull request #204 from antmicro/write_to_flash <enjoy-digital>
    |\
    | * 2ee194b2 - bios: add fw (flash write) command <Mateusz Holenko>
    * | cef23690 - core/spi_flash: re-integrate bitbang write support <Florent Kermarrec>
    |/
    * 5cc4c334 - README: remove LiteUSB (deprecated) <Florent Kermarrec>
    * dc03b7fa - boards: community supported boards are now located at https://github.com/litex-hub/litex-boards <Florent Kermarrec>
    * 0af017e6 - liteeth: update mac imports (olds still works, but that's now the prefered way) <Florent Kermarrec>
    * ecf999b8 - soc/cores: add usb_fifo with FT245 USB FIFO PHY from LiteUSB, deprecate LiteUSB <Florent Kermarrec>
    * e667d5ae - README: update Intro <Florent Kermarrec>
    * 8f6e66ca - make sure #!/usr/bin/env python3 is before copyright header <Florent Kermarrec>
    * c7f36ab0 - test: add copyright header <Florent Kermarrec>
    * daa4307d - add CONTRIBUTORS file and add copyright header to all files <Florent Kermarrec>
    * 361f9d0d - bios/sdram: set init_done/error when DDRCTRL is present (litedram_gen) <Florent Kermarrec>
    * d8ac9362 - Convert top level comment to a docstring. <Tim 'mithro' Ansell>
    *   45632c66 - Merge pull request #202 from xobs/add-up5kspram <enjoy-digital>
    |\
    | * 7656f54d - soc: cores: add up5kspram module <William D. Jones>
    |/
    * 73dbffe8 - cores/frequency_meter: allow passing clk to be measured as a parameter <Florent Kermarrec>
    *   408d3f1f - Merge pull request #201 from gsomlo/gls-fix-initmem <enjoy-digital>
    |\
    | * ab827d21 - tools/litex_sim: fix default endianness for mem_init <Gabriel L. Somlo>
    |/
    *   f47b4902 - Merge pull request #200 from gsomlo/gls-rocket-variants <enjoy-digital>
    |\
    | * f75863fc - cpu/rocket: add "linux" (MMU) and "full" (MMU & FPU) variants <Gabriel L. Somlo>
    |/
    * c0df9e08 - cpu/rocket: update submodule <Florent Kermarrec>
    * 87118d50 - integration/soc_core: move cpu_variant checks/formating to cpu <Florent Kermarrec>
    * f6b67a6d - cpu/vexriscv: add "linux+no-dsp" variant <Florent Kermarrec>
    * 95b1b454 - cpu/vexriscv: update <Florent Kermarrec>
    * e46d287b - targets/ulx3s: use CAS latency of 3 to be compatible with production boards <Florent Kermarrec>

 * litex-renode changed from bd1d0a0 to a57aa47
    *   a57aa47 - Merge pull request #8 from antmicro/newest_litex_fixes <Tim Ansell>
    |\
    | * aebbe7f - Rework obtaining system clock frequency. <Mateusz Holenko>
    | * bd77b6c - Do not generate `csr` memory region. <Mateusz Holenko>
    |/
    * 0d3b303 - Merge pull request #7 from antmicro/support_more_peripherals <Tim Ansell>
    * 406eafb - Fix generation of SPI flash peripheral. <Mateusz Holenko>
    * ab22e8f - Change VexRiscv configuration. <Mateusz Holenko>
    * f799d28 - Generate `cpu` (CPU timer) peripheral. <Mateusz Holenko>
    * c2bea62 - Allow to set custom interrupts. <Mateusz Holenko>
    * 66a4add - Allow to override the peripheral name. <Mateusz Holenko>
    * 409b696 - Generate `cas` (Control And Status) peripheral. <Mateusz Holenko>
    * ae3bee6 - Generate `ethphy` peripheral. <Mateusz Holenko>

 * migen changed from 0.6.dev-283-g562c046 to 0.6.dev-289-g5585912
    * 5585912 - cdc: avoid race between data and request in BusSynchronizer <Sebastien Bourdeauducq>
    * f4979a2 - cdc: add BlindTransfer (from artiq.rtio.cdc) <Sebastien Bourdeauducq>
    * dd4ed5d - lattice/diamond: remove source/toolchain_path <Sebastien Bourdeauducq>
    * b0d9a18 - fix ISE build <Sebastien Bourdeauducq>
    * caab414 - build: remove tool version detection and sourcing of vendor script <Sebastien Bourdeauducq>
    * 5c5486b - xilinx: work around Vivado locale bug. Closes #183 <Sebastien Bourdeauducq>

Full submodule status
--
 42f5fa4ed99b669da4b4169a42eca7dbf5a293c7 edid-decode (remotes/origin/HEAD)
 1c21ee44a2b3936f62e4b43f2bcbf63ce9404691 flash_proxies (heads/master)
 6c53996a7042050def908882b36e92585b6ef138 litedram (remotes/origin/HEAD)
 ad187d35f2b967eb152adcc9f1998a914e5bb53a liteeth (heads/master)
 71c9a3a2eeaae8c4c44ffae14fb5417b94319206 litepcie (remotes/origin/HEAD)
 db5d2f7881161ce5b9a10a0ab42555f884b9d7c1 litesata (heads/master)
 9e3b9d84ce6d0e895d0ac275df78ccbd0e0e0ab2 litescope (heads/master)
 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (heads/master)
 98e145fba8c25394e9958bad67e2a457d145127e litevideo (heads/master)
 e637aa657b7c1163c7c21c4b972f4aa947406272 litex (remotes/origin/HEAD)
 a57aa47ff6863f08d75d33fb5545ea489817ac0d litex-renode (remotes/origin/HEAD)
 558591288dd08302cb8830310ba6975757b58c72 migen (0.6.dev-289-g5585912)

Author: mateusz-holenko