9 files changed
+9
-9
lines changedSubmodule flash_proxies updated from c506426 to a628956
- .gitignore+89-5
- LICENSE+3-3
- README+29-19
- litedram/common.py+6-6
- litedram/core/bankmachine.py+2-2
- litedram/core/controller.py+1-1
- litedram/core/multiplexer.py+2-2
- litedram/core/perf.py+1-1
- litedram/core/refresher.py+2-2
- litedram/dfii.py+1-1
- litedram/frontend/adaptation.py+1-1
- litedram/frontend/bist.py+2-2
- litedram/frontend/bridge.py+1-1
- litedram/frontend/crossbar.py+2-2
- litedram/frontend/dma.py+3-3
- litedram/modules.py+16-1
- litedram/phy/a7ddrphy.py+4-2
- litedram/phy/dfi.py+7-7
- litedram/phy/gensdrphy.py+3-3
- litedram/phy/k7ddrphy.py+1-1
- litedram/phy/kusddrphy.py+2-2
- litedram/phy/model.py+1-1
- litedram/phy/s6ddrphy.py+3-3
- setup.py+4-4
- test/common.py+1-1
- test/test_bist.py+1-1
- test/test_bist_async.py+1-1
- test/test_downconverter.py+1-1
- test/test_upconverter.py+2-2
- .gitignore+30
- LICENSE+1-1
- README+35-50
- example_designs/make.py+2-2
- example_designs/targets/base.py+1-1
- example_designs/targets/core.py+1-1
- liteeth/common.py+1-1
- liteeth/core/arp.py+2-1
- liteeth/core/mac/core.py+2-1
- liteeth/core/mac/crc.py+6-5
- liteeth/core/mac/preamble.py+1-1
- liteeth/core/mac/wishbone.py+2-1
- liteeth/phy/common.py+2-2
- liteeth/phy/gmii.py+2-2
- liteeth/phy/gmii_mii.py+2-2
- liteeth/phy/mii.py+1-1
- liteeth/phy/rmii.py+4-4
- liteeth/phy/s6rgmii.py+4-4
- liteeth/phy/s7rgmii.py+4-4
- setup.py+4-4
- test/test_arp.py+2-1
- test/test_etherbone.py+2-1
- test/test_icmp.py+2-1
- test/test_ip.py+2-1
- test/test_mac_core.py+2-1
- test/test_mac_wishbone.py+2-1
- test/test_udp.py+2-1
- .gitignore+89-5
- LICENSE+1-1
- README+27-43
- example_designs/make.py+2-2
- example_designs/targets/dma.py+10-13
- litepcie/common.py+1-1
- litepcie/core/common.py+1-1
- litepcie/core/crossbar.py+1-1
- litepcie/core/endpoint.py+1-1
- litepcie/core/msi.py+1-1
- litepcie/core/tlp/common.py+1-1
- litepcie/core/tlp/controller.py+2-3
- litepcie/core/tlp/depacketizer.py+92-52
- litepcie/core/tlp/packetizer.py+119-41
- litepcie/core/tlp/reordering.py+1-1
- litepcie/frontend/dma.py+26-22
- litepcie/frontend/wishbone.py+1-1
- litepcie/phy/s7pciephy.py+5-3
- litepcie/phy/xilinx/7-series/artix7/pcie_core_top.v+118-58
- litepcie/phy/xilinx/7-series/common/pcie.v+28-10
- litepcie/phy/xilinx/7-series/common/pcie_axi_basic_rx.v+1-1
- litepcie/phy/xilinx/7-series/common/pcie_axi_basic_rx_null_gen.v+1-1
- litepcie/phy/xilinx/7-series/common/pcie_axi_basic_rx_pipeline.v+1-1
- litepcie/phy/xilinx/7-series/common/pcie_axi_basic_top.v+1-1
- litepcie/phy/xilinx/7-series/common/pcie_axi_basic_tx.v+1-1
- litepcie/phy/xilinx/7-series/common/pcie_axi_basic_tx_pipeline.v+1-1
- litepcie/phy/xilinx/7-series/common/pcie_axi_basic_tx_thrtl_ctl.v+2-1
- litepcie/phy/xilinx/7-series/common/pcie_gt_common.v+5-3
- litepcie/phy/xilinx/7-series/common/pcie_gt_rx_valid_filter_7x.v+1-1
- litepcie/phy/xilinx/7-series/common/pcie_gt_top.v+151-150
- litepcie/phy/xilinx/7-series/common/pcie_gt_wrapper.v+7-11
- litepcie/phy/xilinx/7-series/common/pcie_gtp_cpllpd_ovrd.v+1-1
- litepcie/phy/xilinx/7-series/common/pcie_gtp_pipe_drp.v+4-4
- litepcie/phy/xilinx/7-series/common/pcie_gtp_pipe_rate.v+1-1
- litepcie/phy/xilinx/7-series/common/pcie_gtp_pipe_reset.v+1-1
- litepcie/phy/xilinx/7-series/common/pcie_gtx_cpllpd_ovrd.v+1-1
- litepcie/phy/xilinx/7-series/common/pcie_pcie2_top.v+65-60
- litepcie/phy/xilinx/7-series/common/pcie_pcie_7x.v+12-2
- litepcie/phy/xilinx/7-series/common/pcie_pcie_bram_7x.v+1-1
- litepcie/phy/xilinx/7-series/common/pcie_pcie_bram_top_7x.v+1-1
- litepcie/phy/xilinx/7-series/common/pcie_pcie_brams_7x.v+1-1
- litepcie/phy/xilinx/7-series/common/pcie_pcie_pipe_lane.v+1-1
- litepcie/phy/xilinx/7-series/common/pcie_pcie_pipe_misc.v+1-1
- litepcie/phy/xilinx/7-series/common/pcie_pcie_pipe_pipeline.v+1-1
- litepcie/phy/xilinx/7-series/common/pcie_pcie_top.v+20-3
- litepcie/phy/xilinx/7-series/common/pcie_phy.v+15-14
- litepcie/phy/xilinx/7-series/common/pcie_pipe_clock.v+42-19
- litepcie/phy/xilinx/7-series/common/pcie_pipe_drp.v+1-1
- litepcie/phy/xilinx/7-series/common/pcie_pipe_eq.v+1-1
- litepcie/phy/xilinx/7-series/common/pcie_pipe_rate.v+1-1
- litepcie/phy/xilinx/7-series/common/pcie_pipe_reset.v+1-1
- litepcie/phy/xilinx/7-series/common/pcie_pipe_sync.v+1-1
- litepcie/phy/xilinx/7-series/common/pcie_pipe_user.v+1-1
- litepcie/phy/xilinx/7-series/common/pcie_pipe_wrapper.v+512-501
- litepcie/phy/xilinx/7-series/common/pcie_qpll_drp.v+1-1
- litepcie/phy/xilinx/7-series/common/pcie_qpll_reset.v+1-1
- litepcie/phy/xilinx/7-series/common/pcie_qpll_wrapper.v+83-86
- litepcie/phy/xilinx/7-series/common/pcie_rxeq_scan.v+1-1
- litepcie/phy/xilinx/7-series/common/pcie_support.v+11-4
- litepcie/phy/xilinx/7-series/common/xpm_cdc.sv+1.3k
- setup.py+3-3
- test/model/phy.py+1-1
- test/test_dma.py+6-17
- test/test_wishbone.py+2-1
- .gitignore+89-5
- LICENSE+2-3
- README+16-47
- example_designs/make.py+2-2
- example_designs/targets/bist.py+2-2
- example_designs/targets/core.py+1-1
- example_designs/targets/mirroring.py+2-2
- example_designs/targets/striping.py+3-3
- litesata/common.py+1-1
- litesata/frontend/arbitration.py+1-1
- litesata/phy/ctrl.py+1-1
- litesata/phy/datapath.py+1-1
- litesata/phy/k7/crg.py+5-5
- litesata/phy/k7/trx.py+2-2
- setup.py+5-4
Submodule liteusb updated from 0b05b6c to 23d6a68
Submodule litevideo updated from 9907975 to 18b88df
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