Merge pull request #252 from mithro/spi

mithro · mithro · commit 0d326d443b54 · 2016-04-16T13:32:23.000+10:00
Adding support for SPI flash on Pipistrello and Opsis board. Working on #237
diff --git a/platforms/opsis.py b/platforms/opsis.py
@@ -357,9 +357,27 @@ class Platform(XilinxPlatform):
     default_clk_period = 10.0
     hdmi_infos = _hdmi_infos
 
+    # W25Q128FVEIG - component U3
+    # 128M (16M x 8) - 104MHz
+    # Pretends to be a Micron N25Q128 (ID 0x0018ba20)
+    # FIXME: Create a "spi flash module" object in the same way we have SDRAM
+    # module objects.
+    spiflash_read_dummy_bits = 10
+    spiflash_clock_div = 4
+    spiflash_total_size = int((128/8)*1024*1024) # 128Mbit
+    spiflash_page_size = 256
+    spiflash_sector_size = 0x10000
+
+
+    # The Opsis has a XC6SLX45 which bitstream takes up ~12Mbit (1484472 bytes)
+    # 0x200000 offset (16Mbit) gives plenty of space
+    gateware_size = 0x200000
+
+
     def __init__(self, programmer="openocd"):
         # XC6SLX45T-3FGG484C
         XilinxPlatform.__init__(self,  "xc6slx45t-fgg484-3", _io, _connectors)
+        self.programmer = programmer
 
         pins = {
           'ProgPin': 'PullUp',
@@ -373,15 +391,14 @@ def __init__(self, programmer="openocd"):
         for pin, config in pins.items():
             self.toolchain.bitgen_opt += " -g %s:%s " % (pin, config)
 
-        self.programmer = programmer
-
         # FPGA AUX is connected to the 3.3V supply
         self.add_platform_command("""CONFIG VCCAUX="3.3";""")
 
     def create_programmer(self):
 	# Preferred programmer - Needs ixo-usb-jtag and latest openocd.
+        proxy="bscan_spi_{}.bit".format(self.device.split('-')[0])
         if self.programmer == "openocd":
-            return OpenOCD(config="board/numato_opsis.cfg")
+            return OpenOCD(config="board/numato_opsis.cfg", flash_proxy_basename=proxy)
 	# Alternative programmers - not regularly tested.
         elif self.programmer == "urjtag":
             return UrJTAG(cable="USBBlaster")
diff --git a/platforms/pipistrello.py b/platforms/pipistrello.py
@@ -0,0 +1,169 @@
+from mibuild.generic_platform import *
+from mibuild.xilinx import XilinxPlatform
+
+from mibuild.openocd import OpenOCD
+# Alternative programmers
+from mibuild.xilinx import UrJTAG
+from mibuild.xilinx.programmer import XC3SProg
+
+_io = [
+    ("user_led", 0, Pins("V16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")),  # green at hdmi
+    ("user_led", 1, Pins("U16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")),  # red at hdmi
+    ("user_led", 2, Pins("A16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")),  # green at msd
+    ("user_led", 3, Pins("A15"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")),  # red at msd
+    ("user_led", 4, Pins("A12"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")),  # red at usb
+
+    ("user_btn", 0, Pins("N14"), IOStandard("LVTTL"), Misc("PULLDOWN")),
+
+    ("clk50", 0, Pins("H17"), IOStandard("LVTTL")),
+
+    ("serial", 0,
+        Subsignal("tx", Pins("A10")),
+        Subsignal("rx", Pins("A11"), Misc("PULLUP")),
+        Subsignal("cts", Pins("C10"), Misc("PULLUP")),
+        Subsignal("rts", Pins("A9"), Misc("PULLUP")),
+        IOStandard("LVTTL"),
+    ),
+
+    ("usb_fifo", 0,
+        Subsignal("data", Pins("A11 A10 C10 A9 B9 A8 B8 A7")),
+        Subsignal("rxf_n", Pins("C7")),
+        Subsignal("txe_n", Pins("A6")),
+        Subsignal("rd_n", Pins("B6")),
+        Subsignal("wr_n", Pins("A5")),
+        Subsignal("siwua", Pins("C5")),
+        IOStandard("LVTTL"),
+    ),
+
+    ("hdmi", 0,
+        Subsignal("clk_p", Pins("U5"), IOStandard("TMDS_33")),
+        Subsignal("clk_n", Pins("V5"), IOStandard("TMDS_33")),
+        Subsignal("data0_p", Pins("T6"), IOStandard("TMDS_33")),
+        Subsignal("data0_n", Pins("V6"), IOStandard("TMDS_33")),
+        Subsignal("data1_p", Pins("U7"), IOStandard("TMDS_33")),
+        Subsignal("data1_n", Pins("V7"), IOStandard("TMDS_33")),
+        Subsignal("data2_p", Pins("U8"), IOStandard("TMDS_33")),
+        Subsignal("data2_n", Pins("V8"), IOStandard("TMDS_33")),
+        Subsignal("scl", Pins("V9"), IOStandard("I2C")),
+        Subsignal("sda", Pins("T9"), IOStandard("I2C")),
+        Subsignal("hpd_notif", Pins("R8"), IOStandard("LVTTL")),
+    ),
+
+    ("spiflash", 0,
+        Subsignal("cs_n", Pins("V3")),
+        Subsignal("clk", Pins("R15")),
+        Subsignal("mosi", Pins("T13")),
+        Subsignal("miso", Pins("R13"), Misc("PULLUP")),
+        Subsignal("wp", Pins("T14")),
+        Subsignal("hold", Pins("V14")),
+        IOStandard("LVTTL"), Misc("SLEW=FAST")
+    ),
+
+    ("spiflash2x", 0,
+        Subsignal("cs_n", Pins("V3")),
+        Subsignal("clk", Pins("R15")),
+        Subsignal("dq", Pins("T13 R13"), Misc("PULLUP")),
+        Subsignal("wp", Pins("T14")),
+        Subsignal("hold", Pins("V14")),
+        IOStandard("LVTTL"), Misc("SLEW=FAST")
+    ),
+
+    ("spiflash4x", 0,
+        Subsignal("cs_n", Pins("V3")),
+        Subsignal("clk", Pins("R15")),
+        Subsignal("dq", Pins("T13 R13 T14 V14"), Misc("PULLUP")),
+        IOStandard("LVTTL"), Misc("SLEW=FAST")
+    ),
+
+    ("mmc", 0,
+        Subsignal("clk", Pins("A3")),
+        Subsignal("cmd", Pins("B3"), Misc("PULLUP")),
+        Subsignal("dat", Pins("B4 A4 B2 A2"), Misc("PULLUP")),
+        IOStandard("SDIO")
+    ),
+
+    ("mmc_spi", 0,
+        Subsignal("cs_n", Pins("A2"), Misc("PULLUP")),
+        Subsignal("clk", Pins("A3")),
+        Subsignal("mosi", Pins("B3")),
+        Subsignal("miso", Pins("B4"), Misc("PULLUP")),
+        IOStandard("SDIO")
+    ),
+
+    ("audio", 0,
+        Subsignal("l", Pins("R7"), Misc("SLEW=SLOW")),
+        Subsignal("r", Pins("T7"), Misc("SLEW=SLOW")),
+        IOStandard("LVTTL"),
+    ),
+
+    ("pmod", 0,
+        Subsignal("d", Pins("D9 C8 D6 C4 B11 C9 D8 C6")),
+        IOStandard("LVTTL")
+    ),
+
+    ("ddram_clock", 0,
+        Subsignal("p", Pins("G3")),
+        Subsignal("n", Pins("G1")),
+        IOStandard("MOBILE_DDR")
+    ),
+
+    ("ddram", 0,
+        Subsignal("a", Pins("J7 J6 H5 L7 F3 H4 H3 H6 D2 D1 F4 D3 G6")),
+        Subsignal("ba", Pins("F2 F1")),
+        Subsignal("cke", Pins("H7")),
+        Subsignal("ras_n", Pins("L5")),
+        Subsignal("cas_n", Pins("K5")),
+        Subsignal("we_n", Pins("E3")),
+        Subsignal("dq", Pins("L2 L1 K2 K1 H2 H1 J3 J1 M3 M1 N2 N1 T2 T1 U2 U1")),
+        Subsignal("dqs", Pins("L4 P2")),
+        Subsignal("dm", Pins("K3 K4")),
+        IOStandard("MOBILE_DDR")
+    )
+]
+
+_connectors = [
+    ("A", "U18 T17 P17 P16 N16 N17 M16 L15 L17 K15 K17 J16 H15 H18 F18 D18"),
+    ("B", "C18 E18 G18 H16 J18 K18 K16 L18 L16 M18 N18 N15 P15 P18 T18 U17"),
+    ("C", "F17 F16 E16 G16 F15 G14 F14 H14 H13 J13 G13 H12 K14 K13 K12 L12"),
+]
+
+
+_hdmi_infos = {
+    "HDMI_OUT0_MNEMONIC": "J4",
+    "HDMI_OUT0_DESCRIPTION" : (
+      "  Type A connector, marked as J4.\\r\\n"
+    )
+}
+class Platform(XilinxPlatform):
+    identifier = 0x5049
+    default_clk_name = "clk50"
+    default_clk_period = 20
+    hdmi_infos = _hdmi_infos
+
+    # Micron N25Q128 (ID 0x0018ba20)
+    # FIXME: Create a "spi flash module" object in the same way we have SDRAM
+    # module objects.
+    spiflash_read_dummy_bits = 10
+    spiflash_clock_div = 4
+    spiflash_total_size = int((128/8)*1024*1024) # 128Mbit
+    spiflash_page_size = 256
+    spiflash_sector_size = 0x10000
+
+    # The Pipistrello has a XC6SLX45 which bitstream takes up ~12Mbit (1484472 bytes)
+    # 0x200000 offset (16Mbit) gives plenty of space
+    gateware_size = 0x200000
+
+    def __init__(self, programmer="openocd"):
+        XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors)
+        self.toolchain.bitgen_opt += " -g Compress -g ConfigRate:6"
+        self.programmer = programmer
+
+    def create_programmer(self):
+        proxy="bscan_spi_{}.bit".format(self.device.split('-')[0])
+        if self.programmer == "openocd":
+            return OpenOCD(config="board/pipistrello.cfg", flash_proxy_basename=proxy)
+	# Alternative programmers - not regularly tested.
+        elif self.programmer == "xc3sprog":
+            return XC3SProg("papilio", "bscan_spi_lx45_csg324.bit")
+        else:
+            raise ValueError("{} programmer is not supported".format(self.programmer))
diff --git a/targets/opsis_base.py b/targets/opsis_base.py
@@ -9,6 +9,7 @@
 from migen.genlib.record import Record
 
 from misoclib.com import gpio
+from misoclib.mem.flash import spiflash
 from misoclib.mem.sdram.module import MT41J128M16
 from misoclib.mem.sdram.phy import s6ddrphy
 from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
@@ -135,6 +136,7 @@ class BaseSoC(SDRAMSoC):
     default_platform = "opsis"
 
     csr_peripherals = (
+        "spiflash",
         "ddrphy",
         "dna",
         "git_info",
@@ -148,6 +150,7 @@ class BaseSoC(SDRAMSoC):
 
     mem_map = {
         "firmware_ram": 0x20000000,  # (default shadow @0xa0000000)
+        "spiflash":     0x30000000,  # (default shadow @0xb0000000)
     }
     mem_map.update(SDRAMSoC.mem_map)
 
@@ -203,6 +206,13 @@ def __init__(self, platform,
             ]
             self.register_sdram_phy(self.ddrphy)
 
+        self.submodules.spiflash = spiflash.SpiFlash(
+            platform.request("spiflash4x"), dummy=platform.spiflash_read_dummy_bits, div=platform.spiflash_clock_div)
+        self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
+        self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size)
+        self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size
+        self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=platform.gateware_size)
+
         self.specials += Keep(self.crg.cd_sys.clk)
         platform.add_platform_command("""
 NET "{sys_clk}" TNM_NET = "GRPsys_clk";
@@ -222,7 +232,7 @@ class MiniSoC(BaseSoC):
     interrupt_map.update(BaseSoC.interrupt_map)
 
     mem_map = {
-        "ethmac": 0x30000000,  # (shadow @0xb0000000)
+        "ethmac": 0x40000000,  # (shadow @0xc0000000)
     }
     mem_map.update(BaseSoC.mem_map)
 
diff --git a/targets/pipistrello_base.py b/targets/pipistrello_base.py
@@ -1,21 +1,22 @@
+# Support for the Pipistrello - http://pipistrello.saanlima.com/
 from fractions import Fraction
-import struct
 
 from migen.fhdl.std import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 from migen.bus import wishbone
 
 from misoclib.com import gpio
+from misoclib.mem.flash import spiflash
 from misoclib.mem.sdram.module import MT46H32M16
 from misoclib.mem.sdram.phy import s6ddrphy
 from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
-from misoclib.mem.flash import spiflash
 from misoclib.soc.sdram import SDRAMSoC
 
 from gateware import dna
 from gateware import firmware
 from gateware import git_info
 from gateware import hdmi_out
+from gateware import i2c
 from gateware import i2c_hack
 from gateware import platform_info
 
@@ -133,16 +134,18 @@ class BaseSoC(SDRAMSoC):
 
     mem_map = {
         "firmware_ram": 0x20000000,  # (default shadow @0xa0000000)
+        "spiflash": 0x30000000,  # (default shadow @0xb0000000)
     }
     mem_map.update(SDRAMSoC.mem_map)
 
-    def __init__(self, platform, clk_freq=(83 + Fraction(1, 3))*1000*1000,
-                 sdram_controller_settings=LASMIconSettings(l2_size=32,
-                                                            with_bandwidth=True),
-                 firmware_ram_size=0xa000, firmware_filename=None, **kwargs):
+    def __init__(self, platform,
+                 firmware_ram_size=0xa000,
+                 firmware_filename=None,
+                 **kwargs):
+        clk_freq = (83 + Fraction(1, 3))*1000*1000
         SDRAMSoC.__init__(self, platform, clk_freq,
                           integrated_rom_size=0x8000,
-                          sdram_controller_settings=sdram_controller_settings,
+                          sdram_controller_settings=LASMIconSettings(l2_size=32, with_bandwidth=True),
                           **kwargs)
 
         platform.add_extension(PipistrelloCustom)
@@ -169,19 +172,12 @@ def __init__(self, platform, clk_freq=(83 + Fraction(1, 3))*1000*1000,
             ]
             self.register_sdram_phy(self.ddrphy)
 
-        if not self.integrated_rom_size:
-            self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"),
-                                                         dummy=10, div=4)
-            self.add_constant("SPIFLASH_PAGE_SIZE", 256)
-            self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
-            self.flash_boot_address = 0x180000
-            self.register_rom(self.spiflash.bus, 0x1000000)
-        platform.add_platform_command("""PIN "hdmi_out_pix_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;""")
-
-_hdmi_infos = {
-    "HDMI_OUT0_MNEMONIC": "J4",
-    "HDMI_OUT0_DESCRIPTION": "XXX",
-}
+        self.submodules.spiflash = spiflash.SpiFlash(
+            platform.request("spiflash4x"), dummy=platform.spiflash_read_dummy_bits, div=platform.spiflash_clock_div)
+        self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
+        self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size)
+        self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size
+        self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=platform.gateware_size)
 
 
 class VideomixerSoC(BaseSoC):
@@ -196,7 +192,9 @@ def __init__(self, platform, **kwargs):
         self.submodules.hdmi_out0 = hdmi_out.HDMIOut(
             platform.request("hdmi", 0), self.sdram.crossbar.get_master())
 
-        for k, v in _hdmi_infos.items():
+        platform.add_platform_command("""PIN "hdmi_out_pix_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;""")
+
+        for k, v in platform.hdmi_infos.items():
             self.add_constant(k, v)
 
 default_subtarget = VideomixerSoC
