targets: fix csr automatic numbering

enjoy-digital · enjoy-digital · commit 061421e37980 · 2016-01-23T09:28:50.000+01:00
diff --git a/targets/atlys_base.py b/targets/atlys_base.py
@@ -131,7 +131,7 @@ class BaseSoC(SDRAMSoC):
 
     csr_peripherals = (
         "ddrphy",
-        "dna"
+        "dna",
     )
     csr_map_update(SDRAMSoC.csr_map, csr_peripherals)
 
diff --git a/targets/atlys_edid_debug.py b/targets/atlys_edid_debug.py
@@ -27,7 +27,7 @@ def __init__(self):
 
 class EDIDDebugSoC(VideomixerSoC):
     csr_peripherals = (
-        "logic_analyzer"
+        "logic_analyzer",
     )
     csr_map_update(VideomixerSoC.csr_map, csr_peripherals)
 
diff --git a/targets/atlys_hdmi2eth.py b/targets/atlys_hdmi2eth.py
@@ -59,7 +59,7 @@ class VideomixerSoC(EtherboneSoC):
         "hdmi_in0",
         "hdmi_in0_edid_mem",
         "hdmi_in1",
-        "hdmi_in1_edid_mem"
+        "hdmi_in1_edid_mem",
     )
     csr_map_update(EtherboneSoC.csr_map, csr_peripherals)
 
@@ -103,7 +103,7 @@ def __init__(self, platform, **kwargs):
 class HDMI2ETHSoC(VideomixerSoC):
     csr_peripherals = (
         "encoder_reader",
-        "encoder"
+        "encoder",
     )
     csr_map_update(VideomixerSoC.csr_map, csr_peripherals)
     mem_map = {
diff --git a/targets/atlys_hdmi2usb.py b/targets/atlys_hdmi2usb.py
@@ -13,7 +13,7 @@ class VideomixerSoC(BaseSoC):
         "hdmi_in0",
         "hdmi_in0_edid_mem",
         "hdmi_in1",
-        "hdmi_in1_edid_mem"
+        "hdmi_in1_edid_mem",
     )
     csr_map_update(BaseSoC.csr_map, csr_peripherals)
 
@@ -57,7 +57,7 @@ def __init__(self, platform, **kwargs):
 class HDMI2USBSoC(VideomixerSoC):
     csr_peripherals = (
         "encoder_reader",
-        "encoder"
+        "encoder",
     )
     csr_map_update(VideomixerSoC.csr_map, csr_peripherals)
     mem_map = {
diff --git a/targets/opsis_base.py b/targets/opsis_base.py
@@ -153,7 +153,7 @@ class BaseSoC(SDRAMSoC):
         "fx2_reset",
         "fx2_hack",
 #        "opsis_eeprom_i2c",
-        "tofe_eeprom_i2c"
+        "tofe_eeprom_i2c",
     )
     csr_map_update(SDRAMSoC.csr_map, csr_peripherals)
 
@@ -205,7 +205,7 @@ def __init__(self, platform,
 class MiniSoC(BaseSoC):
     csr_peripherals = (
         "ethphy",
-        "ethmac"
+        "ethmac",
     )
     csr_map_update(BaseSoC.csr_map, csr_peripherals)
 
diff --git a/targets/opsis_hdmi2usb.py b/targets/opsis_hdmi2usb.py
@@ -7,15 +7,15 @@
 from gateware.streamer import USBStreamer
 
 class VideomixerSoC(BaseSoC):
-    csr_map = {
-        "hdmi_out0":         21,
-        "hdmi_out1":         22,
-        "hdmi_in0":          23,
-        "hdmi_in0_edid_mem": 24,
-        "hdmi_in1":          25,
-        "hdmi_in1_edid_mem": 26,
-    }
-    csr_map.update(BaseSoC.csr_map)
+    csr_peripherals = (
+        "hdmi_out0",
+        "hdmi_out1",
+        "hdmi_in0",
+        "hdmi_in0_edid_mem",
+        "hdmi_in1",
+        "hdmi_in1_edid_mem",
+    )
+    csr_map_update(BaseSoC.csr_map, csr_peripherals)
 
     interrupt_map = {
         "hdmi_in0": 3,
@@ -57,7 +57,7 @@ def __init__(self, platform, **kwargs):
 class HDMI2USBSoC(VideomixerSoC):
     csr_peripherals = (
         "encoder_reader",
-        "encoder"
+        "encoder",
     )
     csr_map_update(VideomixerSoC.csr_map, csr_peripherals)
     mem_map = {
diff --git a/targets/pipistrello_base.py b/targets/pipistrello_base.py
@@ -137,7 +137,7 @@ class BaseSoC(SDRAMSoC):
         "ddrphy",
         "dna",
         "fx2_reset",
-        "fx2_hack"
+        "fx2_hack",
     )
     csr_map_update(SDRAMSoC.csr_map, csr_peripherals)
 
@@ -195,7 +195,7 @@ def __init__(self, platform, clk_freq=(83 + Fraction(1, 3))*1000*1000,
 class VideomixerSoC(BaseSoC):
 
     csr_peripherals = (
-        "hdmi_out0"
+        "hdmi_out0",
     )
     csr_map_update(BaseSoC.csr_map, csr_peripherals)
 

Original file line number	Diff line number	Diff line change
`@@ -131,7 +131,7 @@ class BaseSoC(SDRAMSoC):`
`131`	`131`
`132`	`132`	`csr_peripherals = (`
`133`	`133`	`"ddrphy",`
`134`		`- "dna"`
	`134`	`+ "dna",`
`135`	`135`	`)`
`136`	`136`	`csr_map_update(SDRAMSoC.csr_map, csr_peripherals)`
`137`	`137`
Original file line number	Diff line number	Diff line change
`@@ -27,7 +27,7 @@ def __init__(self):`
`27`	`27`
`28`	`28`	`class EDIDDebugSoC(VideomixerSoC):`
`29`	`29`	`csr_peripherals = (`
`30`		`- "logic_analyzer"`
	`30`	`+ "logic_analyzer",`
`31`	`31`	`)`
`32`	`32`	`csr_map_update(VideomixerSoC.csr_map, csr_peripherals)`
`33`	`33`
Original file line number	Diff line number	Diff line change
`@@ -137,7 +137,7 @@ class BaseSoC(SDRAMSoC):`
`137`	`137`	`"ddrphy",`
`138`	`138`	`"dna",`
`139`	`139`	`"fx2_reset",`
`140`		`- "fx2_hack"`
	`140`	`+ "fx2_hack",`
`141`	`141`	`)`
`142`	`142`	`csr_map_update(SDRAMSoC.csr_map, csr_peripherals)`
`143`	`143`
`@@ -195,7 +195,7 @@ def __init__(self, platform, clk_freq=(83 + Fraction(1, 3))10001000,`
`195`	`195`	`class VideomixerSoC(BaseSoC):`
`196`	`196`
`197`	`197`	`csr_peripherals = (`
`198`		`- "hdmi_out0"`
	`198`	`+ "hdmi_out0",`
`199`	`199`	`)`
`200`	`200`	`csr_map_update(BaseSoC.csr_map, csr_peripherals)`
`201`	`201`