[cpu]double-trap exception has highest priority

Author: stnolting

docs/datasheet/cpu.adoc

@@ -1298,17 +1298,17 @@ Whenever any trap (synchronous or asynchronous) is taken into M-mode an internal
 only if the triggering trap does not cause a debug-mode entry. It is cleared again when executing an `mret` instruction.
 Hence, this flag indicates "_inside trap_" status when set. If a second _synchronous_ trap occurs while this flag is set,
 a double-trap exception is raised. The RISC-V-compliant "double-trap" exception code 16 (see <<_neorv32_trap_listing>>)
-is used to identify this event. In summary, an trap that is followed by a synchronous trap (without an `mret` in between)
+is used to identify this event. In summary, a trap that is followed by a synchronous trap (without an `mret` in between)
 causes a double-trap exception:
 
 .Double-Trap Scenarios
 [cols="<3,<3,<4"]
 [options="header", grid="rows"]
 |=======================
 | First Trap | Second Trap | Resulting State
-| Synchronous (e.g. `ecall`) | Synchronous (e.g. `ecall`) | **Double-trap**
+| Synchronous (e.g. `ecall`) | Synchronous (e.g. `ecall`) | **Double-trap exception**
 | Synchronous (e.g. `ecall`) | Asynchronous (interrupt)   | Second trap is not triggered; IRQs are automatically disabled upon trap entry (<<_mstatus>>.`MIE` automatically clears)
-| Asynchronous (interrupt)   | Synchronous (e.g. `ecall`) | **Double-trap**
+| Asynchronous (interrupt)   | Synchronous (e.g. `ecall`) | **Double-trap exception**
 | Asynchronous (interrupt)   | Asynchronous (interrupt)   | Second trap is not triggered; IRQs are automatically disabled upon trap entry (<<_mstatus>>.`MIE` automatically clears); see <<_nested_interrupts>>
 |=======================
 
@@ -1363,8 +1363,8 @@ can be used to output debug information, to bring the system into a safe state o
 |=======================
 | Prio. | `mcause`     | RTE Trap ID              | Cause                                | `mepc` | `mtval` | `mtinst` | Note
 8+^| **Exceptions** (_synchronous_ to instruction execution)
-| 1     | `0x00000001` | `TRAP_CODE_I_ACCESS`     | instruction access fault             | I-PC   | 0       | INS      | **fatal**
-| 2     | `0x00000010` | `TRAP_CODE_DOUBLE_TRAP`  | <<_double_trap_exception>>           | I-PC   | 0       | INS      | **fatal**
+| 1     | `0x00000010` | `TRAP_CODE_DOUBLE_TRAP`  | <<_double_trap_exception>>           | I-PC   | 0       | INS      | **fatal**
+| 2     | `0x00000001` | `TRAP_CODE_I_ACCESS`     | instruction access fault             | I-PC   | 0       | INS      | **fatal**
 | 3     | `0x00000002` | `TRAP_CODE_I_ILLEGAL`    | illegal instruction                  | PC     | 0       | INS      |
 | 4     | `0x00000000` | `TRAP_CODE_I_MISALIGNED` | instruction address misaligned       | PC     | 0       | INS      | **fatal**
 | 5     | `0x0000000b` | `TRAP_CODE_MENV_CALL`    | environment call from M-mode         | PC     | 0       | INS      |

rtl/core/neorv32_cpu_control.vhd

@@ -907,8 +907,8 @@ begin
     elsif rising_edge(clk_i) then
       trap_ctrl.cause <= (others => '0'); -- default
       -- standard RISC-V exceptions --
-      if    (trap_ctrl.exc_buf(exc_iaccess_c)  = '1') then trap_ctrl.cause <= trap_iaf_c; -- instruction access fault
-      elsif (trap_ctrl.exc_buf(exc_doublet_c)  = '1') then trap_ctrl.cause <= trap_dbt_c; -- double-trap
+      if    (trap_ctrl.exc_buf(exc_doublet_c)  = '1') then trap_ctrl.cause <= trap_dbt_c; -- double-trap
+      elsif (trap_ctrl.exc_buf(exc_iaccess_c)  = '1') then trap_ctrl.cause <= trap_iaf_c; -- instruction access fault
       elsif (trap_ctrl.exc_buf(exc_illegal_c)  = '1') then trap_ctrl.cause <= trap_iil_c; -- illegal instruction
       elsif (trap_ctrl.exc_buf(exc_ialign_c)   = '1') then trap_ctrl.cause <= trap_ima_c; -- instruction address misaligned
       elsif (trap_ctrl.exc_buf(exc_ecall_c)    = '1') then trap_ctrl.cause <= trap_env_c(6 downto 2) & replicate_f(csr.prv_level, 2); -- environment call (U/M)

rtl/core/neorv32_package.vhd

@@ -29,7 +29,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110702"; -- hardware version
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110703"; -- hardware version
   constant archid_c     : natural := 19; -- official RISC-V architecture ID
   constant XLEN         : natural := 32; -- native data path width