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- docs/datasheet/cpu.adoc+5
- docs/datasheet/soc.adoc+1
- docs/datasheet/soc_dcache.adoc+7-4
- docs/datasheet/soc_icache.adoc+7-4
- docs/datasheet/soc_sysinfo.adoc+4-4
- docs/datasheet/soc_xbus.adoc+23-21
- rtl/core/neorv32_cache.vhd+41-28
- rtl/core/neorv32_package.vhd+2-1
- rtl/core/neorv32_sysinfo.vhd+6-1
- rtl/core/neorv32_top.vhd+6-2
- rtl/system_integration/neorv32_vivado_ip.tcl+1
- rtl/system_integration/neorv32_vivado_ip.vhd+3-1
- rtl/system_integration/xbus2axi4_bridge.vhd+6-2
- sim/neorv32_tb.vhd+2
- sw/lib/include/neorv32_sysinfo.h+8-5
- sw/lib/source/neorv32_aux.c+25-7
- sw/svd/neorv32.svd+2
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