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lines changed- CHANGELOG.md+5-1
- CITATION.cff-10
- README.md+6-8
- docs/datasheet/cpu.adoc+44-20
- docs/datasheet/cpu_csr.adoc+2-2
- docs/datasheet/cpu_isa.adoc+27
- docs/datasheet/on_chip_debugger.adoc+5
- docs/datasheet/soc.adoc+2
- docs/datasheet/soc_tracer.adoc+107-12
- docs/datasheet/soc_uart.adoc+2-2
- docs/figures/neorv32_processor.png
- docs/references/riscv-semihosting.pdf
- docs/userguide/simulating_the_processor.adoc+4-4
- rtl/core/neorv32_cpu.vhd+13-3
- rtl/core/neorv32_cpu_control.vhd+3-2
- rtl/core/neorv32_cpu_decompressor.vhd+93-17
- rtl/core/neorv32_cpu_frontend.vhd+8-4
- rtl/core/neorv32_package.vhd+7-5
- rtl/core/neorv32_top.vhd+20-12
- rtl/core/neorv32_tracer.vhd+331-29
- rtl/core/neorv32_uart.vhd+9-6
- rtl/system_integration/neorv32_vivado_ip.tcl+19-6
- rtl/system_integration/neorv32_vivado_ip.vhd+2
- sim/ghdl.sh-8
- sim/neorv32_tb.vhd+7-3
- sim/sim_uart_rx.vhd+38-36
- sw/common/common.mk+3-3
- sw/example/demo_semihosting/main.c+36-14
- sw/example/demo_semihosting/makefile-3
- sw/example/demo_semihosting/test.data+1-1
- sw/example/demo_tracer/main.c+2-2
- sw/example/demo_tracer/neorv32_tracer.gdb+78
- sw/example/hello_world/makefile+1-1
- sw/example/processor_check/makefile+1-1
- sw/lib/include/neorv32_cpu.h+3-2
- sw/lib/include/neorv32_cpu_csr.h+1
- sw/lib/include/neorv32_semihosting.h+24-2
- sw/lib/source/neorv32_aux.c+1
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