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21 | 21 | "Ethernet0": {
|
22 | 22 | "index": "1,1,1,1",
|
23 | 23 | "lanes": "65,66,67,68",
|
| 24 | + "alias_at_lanes": "Eth1/1, Eth1/2, Eth1/3, Eth1/4", |
24 | 25 | "breakout_modes": {
|
25 | 26 | "1x100G[40G]": ["Eth1"],
|
26 |
| - "2x50G": ["Eth1/1", "Eth1/2"], |
| 27 | + "2x50G": ["Eth1/1", "Eth1/3"], |
27 | 28 | "4x25G[10G]": ["Eth1/1", "Eth1/2", "Eth1/3", "Eth1/4"]
|
28 | 29 | }
|
29 | 30 | },
|
30 | 31 | "Ethernet4": {
|
31 | 32 | "index": "2,2,2,2",
|
32 | 33 | "lanes": "69,70,71,72",
|
| 34 | + "alias_at_lanes": "Eth2/1, Eth2/2, Eth2/3, Eth2/4", |
33 | 35 | "breakout_modes": {
|
34 | 36 | "1x100G[40G]": ["Eth2"],
|
35 |
| - "2x50G": ["Eth2/1", "Eth2/2"], |
| 37 | + "2x50G": ["Eth2/1", "Eth2/3"], |
36 | 38 | "4x25G[10G]": ["Eth2/1", "Eth2/2", "Eth2/3", "Eth2/4"],
|
37 |
| - "1x50G(2)+2x25G(2)": ["Eth2/1", "Eth2/2", "Eth2/3"] |
| 39 | + "1x50G(2)+2x25G(2)": ["Eth2/1", "Eth2/3", "Eth2/4"] |
38 | 40 | }
|
39 | 41 | },
|
40 | 42 | "Ethernet8": {
|
41 | 43 | "index": "3,3,3,3",
|
42 | 44 | "lanes": "73,74,75,76",
|
| 45 | + "alias_at_lanes": "Eth3/1, Eth3/2, Eth3/3, Eth3/4", |
43 | 46 | "breakout_modes": {
|
44 | 47 | "1x100G[40G]": ["Eth3"],
|
45 |
| - "2x50G": ["Eth3/1", "Eth3/2"], |
| 48 | + "2x50G": ["Eth3/1", "Eth3/3"], |
46 | 49 | "4x25G[10G]": ["Eth3/1", "Eth3/2", "Eth3/3", "Eth3/4"],
|
47 |
| - "1x50G(2)+2x25G(2)": ["Eth3/1", "Eth3/2", "Eth3/3"] |
| 50 | + "1x50G(2)+2x25G(2)": ["Eth3/1", "Eth3/3", "Eth3/4"] |
48 | 51 | }
|
49 | 52 | },
|
50 | 53 | "Ethernet12": {
|
51 | 54 | "index": "4,4,4,4",
|
52 | 55 | "lanes": "77,78,79,80",
|
| 56 | + "alias_at_lanes": "Eth4/1, Eth4/2, Eth4/3, Eth4/4", |
53 | 57 | "breakout_modes": {
|
54 | 58 | "1x100G[40G]": ["Eth4"],
|
55 |
| - "2x50G": ["Eth4/1", "Eth4/2"], |
| 59 | + "2x50G": ["Eth4/1", "Eth4/3"], |
56 | 60 | "4x25G[10G]": ["Eth4/1", "Eth1/2", "Eth4/3", "Eth4/4"]
|
57 | 61 | }
|
58 | 62 | }
|
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