|
| 1 | +# CPU queue stats |
| 2 | + |
| 3 | +Network switches and routers typically have one port connected to the CPU (where the control software runs). This port is referenced as a CPU port on this document. Multiple egress queues on the CPU port helps differentiate traffic and avoid one kind of traffic overwhelming the other. Switch control software installs rules that identify control protocol packets and trap them to a particular queue on the CPU port. Please refer to COPP for more details. |
| 4 | + |
| 5 | +The knowledge of various queue statistics help us identify the current health and reason for any packet drops. SONiC already has commands to examine port and queue statistics associated with front panel ports. The same is extended to examine the CPU queue stats. The watermark commands can also be extended to display the buffer utilization associated with these CPU queues (not included in this HLD). |
| 6 | + |
| 7 | +For example the command *show queue counters <port-name>* which displays the below given statistics starts to display CPU queue statistics as well. |
| 8 | + |
| 9 | +``` |
| 10 | +root@sonic:/home/admin# show queue counters Ethernet0 |
| 11 | + Port TxQ Counter/pkts Counter/bytes Drop/pkts Drop/bytes |
| 12 | +--------- ----- -------------- --------------- ----------- ------------ |
| 13 | +Ethernet0 UC0 0 0 0 0 |
| 14 | +Ethernet0 UC1 0 0 0 0 |
| 15 | +Ethernet0 UC2 0 0 0 0 |
| 16 | +Ethernet0 UC3 0 0 0 0 |
| 17 | +Ethernet0 UC4 0 0 0 0 |
| 18 | +Ethernet0 UC5 0 0 0 0 |
| 19 | +Ethernet0 UC6 0 0 0 0 |
| 20 | +Ethernet0 UC7 0 0 0 0 |
| 21 | +Ethernet0 UC8 0 0 0 0 |
| 22 | +Ethernet0 UC9 0 0 0 0 |
| 23 | +Ethernet0 MC10 0 0 0 0 |
| 24 | +Ethernet0 MC11 0 0 0 0 |
| 25 | +Ethernet0 MC12 0 0 0 0 |
| 26 | +Ethernet0 MC13 0 0 0 0 |
| 27 | +Ethernet0 MC14 0 0 0 0 |
| 28 | +Ethernet0 MC15 0 0 0 0 |
| 29 | +Ethernet0 MC16 0 0 0 0 |
| 30 | +Ethernet0 MC17 0 0 0 0 |
| 31 | +Ethernet0 MC18 0 0 0 0 |
| 32 | +Ethernet0 MC19 0 0 0 0 |
| 33 | +``` |
| 34 | + |
| 35 | +On current SONiC code base, the command returns *Port doesn't exist! CPU* as the CPU port is not understood by SONiC. |
| 36 | + |
| 37 | +``` |
| 38 | +root@sonic:/home/admin# show queue counters CPU |
| 39 | +Port doesn't exist! CPU |
| 40 | +``` |
| 41 | + |
| 42 | +The proposed changes make the command return the actual supported CPU queues and its stats. |
| 43 | + |
| 44 | +``` |
| 45 | +root@L15:/home/admin# show queue counters CPU |
| 46 | + Port TxQ Counter/pkts Counter/bytes Drop/pkts Drop/bytes |
| 47 | +------ ----- -------------- --------------- ----------- ------------ |
| 48 | + CPU MC0 0 0 0 0 |
| 49 | + CPU MC1 0 0 0 0 |
| 50 | + CPU MC2 0 0 0 0 |
| 51 | + CPU MC3 0 0 0 0 |
| 52 | + CPU MC4 0 0 0 0 |
| 53 | + CPU MC5 0 0 0 0 |
| 54 | + CPU MC6 0 0 0 0 |
| 55 | + CPU MC7 0 0 0 0 |
| 56 | + CPU MC8 14 1484 0 0 |
| 57 | + CPU MC9 175 63092 0 0 |
| 58 | + CPU MC10 1810 123080 0 0 |
| 59 | + CPU MC11 0 0 0 0 |
| 60 | + CPU MC12 0 0 0 0 |
| 61 | + CPU MC13 0 0 0 0 |
| 62 | + CPU MC14 0 0 0 0 |
| 63 | + CPU MC15 0 0 0 0 |
| 64 | + CPU MC16 75778 6470474 0 0 |
| 65 | + CPU MC17 0 0 0 0 |
| 66 | + CPU MC18 21837 6601410 0 0 |
| 67 | + CPU MC19 0 0 0 0 |
| 68 | + CPU MC20 0 0 0 0 |
| 69 | + CPU MC21 0 0 0 0 |
| 70 | + CPU MC22 0 0 0 0 |
| 71 | + CPU MC23 76 10032 0 0 |
| 72 | + CPU MC24 0 0 0 0 |
| 73 | + CPU MC25 0 0 0 0 |
| 74 | + CPU MC26 0 0 0 0 |
| 75 | + CPU MC27 0 0 0 0 |
| 76 | + CPU MC28 0 0 0 0 |
| 77 | + CPU MC29 0 0 0 0 |
| 78 | + CPU MC30 0 0 0 0 |
| 79 | + CPU MC31 0 0 0 0 |
| 80 | + CPU MC32 0 0 0 0 |
| 81 | + CPU MC33 0 0 0 0 |
| 82 | + CPU MC34 0 0 0 0 |
| 83 | + CPU MC35 0 0 0 0 |
| 84 | + CPU MC36 0 0 0 0 |
| 85 | + CPU MC37 0 0 0 0 |
| 86 | + CPU MC38 0 0 0 0 |
| 87 | + CPU MC39 0 0 0 0 |
| 88 | + CPU MC40 0 0 0 0 |
| 89 | + CPU MC41 0 0 0 0 |
| 90 | + CPU MC42 0 0 0 0 |
| 91 | + CPU MC43 0 0 0 0 |
| 92 | + CPU MC44 0 0 0 0 |
| 93 | + CPU MC45 0 0 0 0 |
| 94 | + CPU MC46 0 0 0 0 |
| 95 | + CPU MC47 0 0 0 0 |
| 96 | +``` |
| 97 | + |
| 98 | + |
| 99 | +The following COUNTER_DB maps include details for the CPU port and queues. |
| 100 | +COUNTERS_PORT_NAME_MAP |
| 101 | +COUNTERS_QUEUE_NAME_MAP |
| 102 | +COUNTERS_QUEUE_PORT_MAP |
| 103 | +COUNTERS_QUEUE_TYPE_MAP |
| 104 | +COUNTERS_QUEUE_INDEX_MAP |
| 105 | + |
| 106 | +Port and queue counters: |
| 107 | +COUNTERS:oid:<port-oid> |
| 108 | +COUNTERS:oid:<queue-oid> |
| 109 | + |
| 110 | + |
| 111 | + |
| 112 | +Minor code changes are made on *sonic-swss* repo to fetch the supported queues on CPU port and update the flex counters-db maps to include CPU port and its queues. Single line changes were made to *sonic-py-swsssdk*, *sonic-snmpagent* and *sonic-utilities* repos to ignore the newly added CPU port while iterating over the front panel ports. *sonic-sairedis* repo changes are made to enable cpu queues on vslib. |
| 113 | +Syncd periodically fetches the CPU port stats, CPU queues stats along with other flex counter stats and updates the counters-DB. |
| 114 | + |
| 115 | +SAI calls: |
| 116 | +get_port_attribute() API with attribute *SAI_PORT_ATTR_QOS_NUMBER_OF_QUEUES* to fetch the number of CPU queues supported by switch and *SAI_PORT_ATTR_QOS_QUEUE_LIST* to fetch the list of CPU queues. |
| 117 | + |
| 118 | +List of PRs associated with this change: |
| 119 | +https://github.com/Azure/sonic-swss/pull/1544 |
| 120 | +https://github.com/Azure/sonic-py-swsssdk/pull/98 |
| 121 | +https://github.com/Azure/sonic-utilities/pull/1314 |
| 122 | +https://github.com/Azure/sonic-snmpagent/pull/182 |
| 123 | +https://github.com/Azure/sonic-sairedis/pull/732 |
| 124 | + |
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