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[RISCV][ISel] Fold FSGNJX idioms (llvm#100718)
This patch folds `fmul X, (fcopysign 1.0, Y)` into `fsgnjx X, Y`. This pattern exists in some graphics applications/math libraries. Alive2: https://alive2.llvm.org/ce/z/epyL33 Since fpimm +1.0 is lowered to a load from constant pool after OpLegalization, I have to introduce a new RISCVISD node FSGNJX and fold this pattern in DAGCombine. Closes dtcxzyw/llvm-opt-benchmark#1072.
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‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 21 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1473,7 +1473,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
14731473
setTargetDAGCombine(ISD::SRA);
14741474

14751475
if (Subtarget.hasStdExtFOrZfinx())
1476-
setTargetDAGCombine({ISD::FADD, ISD::FMAXNUM, ISD::FMINNUM});
1476+
setTargetDAGCombine({ISD::FADD, ISD::FMAXNUM, ISD::FMINNUM, ISD::FMUL});
14771477

14781478
if (Subtarget.hasStdExtZbb())
14791479
setTargetDAGCombine({ISD::UMAX, ISD::UMIN, ISD::SMAX, ISD::SMIN});
@@ -16682,6 +16682,25 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
1668216682
if (SDValue V = combineBinOpOfZExt(N, DAG))
1668316683
return V;
1668416684
break;
16685+
case ISD::FMUL: {
16686+
// fmul X, (copysign 1.0, Y) -> fsgnjx X, Y
16687+
SDValue N0 = N->getOperand(0);
16688+
SDValue N1 = N->getOperand(1);
16689+
if (N0->getOpcode() != ISD::FCOPYSIGN)
16690+
std::swap(N0, N1);
16691+
if (N0->getOpcode() != ISD::FCOPYSIGN)
16692+
return SDValue();
16693+
ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N0->getOperand(0));
16694+
if (!C || !C->getValueAPF().isExactlyValue(+1.0))
16695+
return SDValue();
16696+
EVT VT = N->getValueType(0);
16697+
if (VT.isVector() || !isOperationLegal(ISD::FCOPYSIGN, VT))
16698+
return SDValue();
16699+
SDValue Sign = N0->getOperand(1);
16700+
if (Sign.getValueType() != VT)
16701+
return SDValue();
16702+
return DAG.getNode(RISCVISD::FSGNJX, SDLoc(N), VT, N1, N0->getOperand(1));
16703+
}
1668516704
case ISD::FADD:
1668616705
case ISD::UMAX:
1668716706
case ISD::UMIN:
@@ -20232,6 +20251,7 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
2023220251
NODE_NAME_CASE(FP_EXTEND_BF16)
2023320252
NODE_NAME_CASE(FROUND)
2023420253
NODE_NAME_CASE(FCLASS)
20254+
NODE_NAME_CASE(FSGNJX)
2023520255
NODE_NAME_CASE(FMAX)
2023620256
NODE_NAME_CASE(FMIN)
2023720257
NODE_NAME_CASE(READ_COUNTER_WIDE)

‎llvm/lib/Target/RISCV/RISCVISelLowering.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -128,6 +128,7 @@ enum NodeType : unsigned {
128128
FROUND,
129129

130130
FCLASS,
131+
FSGNJX,
131132

132133
// Floating point fmax and fmin matching the RISC-V instruction semantics.
133134
FMAX, FMIN,

‎llvm/lib/Target/RISCV/RISCVInstrInfoD.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -282,6 +282,7 @@ def : Pat<(fabs FPR64:$rs1), (FSGNJX_D $rs1, $rs1)>;
282282
def : Pat<(riscv_fclass FPR64:$rs1), (FCLASS_D $rs1)>;
283283

284284
def : PatFprFpr<fcopysign, FSGNJ_D, FPR64, f64>;
285+
def : PatFprFpr<riscv_fsgnjx, FSGNJX_D, FPR64, f64>;
285286
def : Pat<(fcopysign FPR64:$rs1, (fneg FPR64:$rs2)), (FSGNJN_D $rs1, $rs2)>;
286287
def : Pat<(fcopysign FPR64:$rs1, FPR32:$rs2), (FSGNJ_D $rs1, (FCVT_D_S $rs2,
287288
FRM_RNE))>;
@@ -318,6 +319,7 @@ def : Pat<(fabs FPR64INX:$rs1), (FSGNJX_D_INX $rs1, $rs1)>;
318319
def : Pat<(riscv_fclass FPR64INX:$rs1), (FCLASS_D_INX $rs1)>;
319320

320321
def : PatFprFpr<fcopysign, FSGNJ_D_INX, FPR64INX, f64>;
322+
def : PatFprFpr<riscv_fsgnjx, FSGNJX_D_INX, FPR64INX, f64>;
321323
def : Pat<(fcopysign FPR64INX:$rs1, (fneg FPR64INX:$rs2)),
322324
(FSGNJN_D_INX $rs1, $rs2)>;
323325
def : Pat<(fcopysign FPR64INX:$rs1, FPR32INX:$rs2),
@@ -355,6 +357,7 @@ def : Pat<(fabs FPR64IN32X:$rs1), (FSGNJX_D_IN32X $rs1, $rs1)>;
355357
def : Pat<(riscv_fclass FPR64IN32X:$rs1), (FCLASS_D_IN32X $rs1)>;
356358

357359
def : PatFprFpr<fcopysign, FSGNJ_D_IN32X, FPR64IN32X, f64>;
360+
def : PatFprFpr<riscv_fsgnjx, FSGNJX_D_IN32X, FPR64IN32X, f64>;
358361
def : Pat<(fcopysign FPR64IN32X:$rs1, (fneg FPR64IN32X:$rs2)),
359362
(FSGNJN_D_IN32X $rs1, $rs2)>;
360363
def : Pat<(fcopysign FPR64IN32X:$rs1, FPR32INX:$rs2),

‎llvm/lib/Target/RISCV/RISCVInstrInfoF.td

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,13 +31,18 @@ def SDT_RISCVFROUND
3131
SDTCisVT<3, XLenVT>]>;
3232
def SDT_RISCVFCLASS
3333
: SDTypeProfile<1, 1, [SDTCisVT<0, XLenVT>, SDTCisFP<1>]>;
34+
def SDT_RISCVFSGNJX
35+
: SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>]>;
3436

3537
def riscv_fclass
3638
: SDNode<"RISCVISD::FCLASS", SDT_RISCVFCLASS>;
3739

3840
def riscv_fround
3941
: SDNode<"RISCVISD::FROUND", SDT_RISCVFROUND>;
4042

43+
def riscv_fsgnjx
44+
: SDNode<"RISCVISD::FSGNJX", SDT_RISCVFSGNJX>;
45+
4146
def riscv_fmv_w_x_rv64
4247
: SDNode<"RISCVISD::FMV_W_X_RV64", SDT_RISCVFMV_W_X_RV64>;
4348
def riscv_fmv_x_anyextw_rv64
@@ -539,8 +544,10 @@ def : Pat<(fabs FPR32INX:$rs1), (FSGNJX_S_INX $rs1, $rs1)>;
539544
def : Pat<(riscv_fclass FPR32INX:$rs1), (FCLASS_S_INX $rs1)>;
540545
} // Predicates = [HasStdExtZfinx]
541546

542-
foreach Ext = FExts in
547+
foreach Ext = FExts in {
543548
defm : PatFprFpr_m<fcopysign, FSGNJ_S, Ext>;
549+
defm : PatFprFpr_m<riscv_fsgnjx, FSGNJX_S, Ext>;
550+
}
544551

545552
let Predicates = [HasStdExtF] in {
546553
def : Pat<(fcopysign FPR32:$rs1, (fneg FPR32:$rs2)), (FSGNJN_S $rs1, $rs2)>;

‎llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -272,6 +272,7 @@ def : Pat<(f16 (fabs FPR16:$rs1)), (FSGNJX_H $rs1, $rs1)>;
272272
def : Pat<(riscv_fclass (f16 FPR16:$rs1)), (FCLASS_H $rs1)>;
273273

274274
def : PatFprFpr<fcopysign, FSGNJ_H, FPR16, f16>;
275+
def : PatFprFpr<riscv_fsgnjx, FSGNJX_H, FPR16, f16>;
275276
def : Pat<(f16 (fcopysign FPR16:$rs1, (f16 (fneg FPR16:$rs2)))), (FSGNJN_H $rs1, $rs2)>;
276277
def : Pat<(f16 (fcopysign FPR16:$rs1, FPR32:$rs2)),
277278
(FSGNJ_H $rs1, (FCVT_H_S $rs2, FRM_DYN))>;
@@ -314,6 +315,7 @@ def : Pat<(fabs FPR16INX:$rs1), (FSGNJX_H_INX $rs1, $rs1)>;
314315
def : Pat<(riscv_fclass FPR16INX:$rs1), (FCLASS_H_INX $rs1)>;
315316

316317
def : PatFprFpr<fcopysign, FSGNJ_H_INX, FPR16INX, f16>;
318+
def : PatFprFpr<riscv_fsgnjx, FSGNJX_H_INX, FPR16INX, f16>;
317319
def : Pat<(fcopysign FPR16INX:$rs1, (fneg FPR16INX:$rs2)), (FSGNJN_H_INX $rs1, $rs2)>;
318320
def : Pat<(fcopysign FPR16INX:$rs1, FPR32INX:$rs2),
319321
(FSGNJ_H_INX $rs1, (FCVT_H_S_INX $rs2, FRM_DYN))>;

‎llvm/test/CodeGen/RISCV/double-arith.ll

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1497,3 +1497,51 @@ define double @fnmsub_d_contract(double %a, double %b, double %c) nounwind {
14971497
%2 = fsub contract double %c, %1
14981498
ret double %2
14991499
}
1500+
1501+
define double @fsgnjx_f64(double %x, double %y) nounwind {
1502+
; CHECKIFD-LABEL: fsgnjx_f64:
1503+
; CHECKIFD: # %bb.0:
1504+
; CHECKIFD-NEXT: fsgnjx.d fa0, fa1, fa0
1505+
; CHECKIFD-NEXT: ret
1506+
;
1507+
; RV32IZFINXZDINX-LABEL: fsgnjx_f64:
1508+
; RV32IZFINXZDINX: # %bb.0:
1509+
; RV32IZFINXZDINX-NEXT: fsgnjx.d a0, a2, a0
1510+
; RV32IZFINXZDINX-NEXT: ret
1511+
;
1512+
; RV64IZFINXZDINX-LABEL: fsgnjx_f64:
1513+
; RV64IZFINXZDINX: # %bb.0:
1514+
; RV64IZFINXZDINX-NEXT: fsgnjx.d a0, a1, a0
1515+
; RV64IZFINXZDINX-NEXT: ret
1516+
;
1517+
; RV32I-LABEL: fsgnjx_f64:
1518+
; RV32I: # %bb.0:
1519+
; RV32I-NEXT: addi sp, sp, -16
1520+
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1521+
; RV32I-NEXT: lui a0, 524288
1522+
; RV32I-NEXT: and a0, a1, a0
1523+
; RV32I-NEXT: lui a1, 261888
1524+
; RV32I-NEXT: or a1, a0, a1
1525+
; RV32I-NEXT: li a0, 0
1526+
; RV32I-NEXT: call __muldf3
1527+
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1528+
; RV32I-NEXT: addi sp, sp, 16
1529+
; RV32I-NEXT: ret
1530+
;
1531+
; RV64I-LABEL: fsgnjx_f64:
1532+
; RV64I: # %bb.0:
1533+
; RV64I-NEXT: addi sp, sp, -16
1534+
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1535+
; RV64I-NEXT: srli a0, a0, 63
1536+
; RV64I-NEXT: slli a0, a0, 63
1537+
; RV64I-NEXT: li a2, 1023
1538+
; RV64I-NEXT: slli a2, a2, 52
1539+
; RV64I-NEXT: or a0, a0, a2
1540+
; RV64I-NEXT: call __muldf3
1541+
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1542+
; RV64I-NEXT: addi sp, sp, 16
1543+
; RV64I-NEXT: ret
1544+
%z = call double @llvm.copysign.f64(double 1.0, double %x)
1545+
%mul = fmul double %z, %y
1546+
ret double %mul
1547+
}

‎llvm/test/CodeGen/RISCV/float-arith.ll

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1195,3 +1195,44 @@ define float @fnmsub_s_contract(float %a, float %b, float %c) nounwind {
11951195
%2 = fsub contract float %c, %1
11961196
ret float %2
11971197
}
1198+
1199+
define float @fsgnjx_f32(float %x, float %y) nounwind {
1200+
; CHECKIF-LABEL: fsgnjx_f32:
1201+
; CHECKIF: # %bb.0:
1202+
; CHECKIF-NEXT: fsgnjx.s fa0, fa1, fa0
1203+
; CHECKIF-NEXT: ret
1204+
;
1205+
; CHECKIZFINX-LABEL: fsgnjx_f32:
1206+
; CHECKIZFINX: # %bb.0:
1207+
; CHECKIZFINX-NEXT: fsgnjx.s a0, a1, a0
1208+
; CHECKIZFINX-NEXT: ret
1209+
;
1210+
; RV32I-LABEL: fsgnjx_f32:
1211+
; RV32I: # %bb.0:
1212+
; RV32I-NEXT: addi sp, sp, -16
1213+
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1214+
; RV32I-NEXT: lui a2, 524288
1215+
; RV32I-NEXT: and a0, a0, a2
1216+
; RV32I-NEXT: lui a2, 260096
1217+
; RV32I-NEXT: or a0, a0, a2
1218+
; RV32I-NEXT: call __mulsf3
1219+
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1220+
; RV32I-NEXT: addi sp, sp, 16
1221+
; RV32I-NEXT: ret
1222+
;
1223+
; RV64I-LABEL: fsgnjx_f32:
1224+
; RV64I: # %bb.0:
1225+
; RV64I-NEXT: addi sp, sp, -16
1226+
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1227+
; RV64I-NEXT: lui a2, 524288
1228+
; RV64I-NEXT: and a0, a0, a2
1229+
; RV64I-NEXT: lui a2, 260096
1230+
; RV64I-NEXT: or a0, a0, a2
1231+
; RV64I-NEXT: call __mulsf3
1232+
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1233+
; RV64I-NEXT: addi sp, sp, 16
1234+
; RV64I-NEXT: ret
1235+
%z = call float @llvm.copysign.f32(float 1.0, float %x)
1236+
%mul = fmul float %z, %y
1237+
ret float %mul
1238+
}

‎llvm/test/CodeGen/RISCV/half-arith.ll

Lines changed: 109 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3104,3 +3104,112 @@ define half @fnmsub_s_contract(half %a, half %b, half %c) nounwind {
31043104
%2 = fsub contract half %c, %1
31053105
ret half %2
31063106
}
3107+
3108+
define half @fsgnjx_f16(half %x, half %y) nounwind {
3109+
; CHECKIZFH-LABEL: fsgnjx_f16:
3110+
; CHECKIZFH: # %bb.0:
3111+
; CHECKIZFH-NEXT: fsgnjx.h fa0, fa1, fa0
3112+
; CHECKIZFH-NEXT: ret
3113+
;
3114+
; CHECK-ZHINX-LABEL: fsgnjx_f16:
3115+
; CHECK-ZHINX: # %bb.0:
3116+
; CHECK-ZHINX-NEXT: fsgnjx.h a0, a1, a0
3117+
; CHECK-ZHINX-NEXT: ret
3118+
;
3119+
; RV32I-LABEL: fsgnjx_f16:
3120+
; RV32I: # %bb.0:
3121+
; RV32I-NEXT: addi sp, sp, -16
3122+
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3123+
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
3124+
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
3125+
; RV32I-NEXT: li a2, 15
3126+
; RV32I-NEXT: slli a2, a2, 10
3127+
; RV32I-NEXT: or s1, a0, a2
3128+
; RV32I-NEXT: slli a0, a1, 16
3129+
; RV32I-NEXT: srli a0, a0, 16
3130+
; RV32I-NEXT: call __extendhfsf2
3131+
; RV32I-NEXT: mv s0, a0
3132+
; RV32I-NEXT: lui a0, 12
3133+
; RV32I-NEXT: addi a0, a0, -1024
3134+
; RV32I-NEXT: and a0, s1, a0
3135+
; RV32I-NEXT: call __extendhfsf2
3136+
; RV32I-NEXT: mv a1, s0
3137+
; RV32I-NEXT: call __mulsf3
3138+
; RV32I-NEXT: call __truncsfhf2
3139+
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3140+
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
3141+
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
3142+
; RV32I-NEXT: addi sp, sp, 16
3143+
; RV32I-NEXT: ret
3144+
;
3145+
; RV64I-LABEL: fsgnjx_f16:
3146+
; RV64I: # %bb.0:
3147+
; RV64I-NEXT: addi sp, sp, -32
3148+
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
3149+
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
3150+
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
3151+
; RV64I-NEXT: li a2, 15
3152+
; RV64I-NEXT: slli a2, a2, 10
3153+
; RV64I-NEXT: or s1, a0, a2
3154+
; RV64I-NEXT: slli a0, a1, 48
3155+
; RV64I-NEXT: srli a0, a0, 48
3156+
; RV64I-NEXT: call __extendhfsf2
3157+
; RV64I-NEXT: mv s0, a0
3158+
; RV64I-NEXT: lui a0, 12
3159+
; RV64I-NEXT: addiw a0, a0, -1024
3160+
; RV64I-NEXT: and a0, s1, a0
3161+
; RV64I-NEXT: call __extendhfsf2
3162+
; RV64I-NEXT: mv a1, s0
3163+
; RV64I-NEXT: call __mulsf3
3164+
; RV64I-NEXT: call __truncsfhf2
3165+
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
3166+
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
3167+
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
3168+
; RV64I-NEXT: addi sp, sp, 32
3169+
; RV64I-NEXT: ret
3170+
;
3171+
; CHECK-RV32-FSGNJ-LABEL: fsgnjx_f16:
3172+
; CHECK-RV32-FSGNJ: # %bb.0:
3173+
; CHECK-RV32-FSGNJ-NEXT: addi sp, sp, -16
3174+
; CHECK-RV32-FSGNJ-NEXT: lui a0, %hi(.LCPI23_0)
3175+
; CHECK-RV32-FSGNJ-NEXT: flh fa5, %lo(.LCPI23_0)(a0)
3176+
; CHECK-RV32-FSGNJ-NEXT: fsh fa0, 12(sp)
3177+
; CHECK-RV32-FSGNJ-NEXT: fsh fa5, 8(sp)
3178+
; CHECK-RV32-FSGNJ-NEXT: lbu a0, 13(sp)
3179+
; CHECK-RV32-FSGNJ-NEXT: lbu a1, 9(sp)
3180+
; CHECK-RV32-FSGNJ-NEXT: andi a0, a0, 128
3181+
; CHECK-RV32-FSGNJ-NEXT: andi a1, a1, 127
3182+
; CHECK-RV32-FSGNJ-NEXT: or a0, a1, a0
3183+
; CHECK-RV32-FSGNJ-NEXT: sb a0, 9(sp)
3184+
; CHECK-RV32-FSGNJ-NEXT: flh fa5, 8(sp)
3185+
; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa4, fa1
3186+
; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa5, fa5
3187+
; CHECK-RV32-FSGNJ-NEXT: fmul.s fa5, fa5, fa4
3188+
; CHECK-RV32-FSGNJ-NEXT: fcvt.h.s fa0, fa5
3189+
; CHECK-RV32-FSGNJ-NEXT: addi sp, sp, 16
3190+
; CHECK-RV32-FSGNJ-NEXT: ret
3191+
;
3192+
; CHECK-RV64-FSGNJ-LABEL: fsgnjx_f16:
3193+
; CHECK-RV64-FSGNJ: # %bb.0:
3194+
; CHECK-RV64-FSGNJ-NEXT: addi sp, sp, -16
3195+
; CHECK-RV64-FSGNJ-NEXT: lui a0, %hi(.LCPI23_0)
3196+
; CHECK-RV64-FSGNJ-NEXT: flh fa5, %lo(.LCPI23_0)(a0)
3197+
; CHECK-RV64-FSGNJ-NEXT: fsh fa0, 8(sp)
3198+
; CHECK-RV64-FSGNJ-NEXT: fsh fa5, 0(sp)
3199+
; CHECK-RV64-FSGNJ-NEXT: lbu a0, 9(sp)
3200+
; CHECK-RV64-FSGNJ-NEXT: lbu a1, 1(sp)
3201+
; CHECK-RV64-FSGNJ-NEXT: andi a0, a0, 128
3202+
; CHECK-RV64-FSGNJ-NEXT: andi a1, a1, 127
3203+
; CHECK-RV64-FSGNJ-NEXT: or a0, a1, a0
3204+
; CHECK-RV64-FSGNJ-NEXT: sb a0, 1(sp)
3205+
; CHECK-RV64-FSGNJ-NEXT: flh fa5, 0(sp)
3206+
; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa4, fa1
3207+
; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa5, fa5
3208+
; CHECK-RV64-FSGNJ-NEXT: fmul.s fa5, fa5, fa4
3209+
; CHECK-RV64-FSGNJ-NEXT: fcvt.h.s fa0, fa5
3210+
; CHECK-RV64-FSGNJ-NEXT: addi sp, sp, 16
3211+
; CHECK-RV64-FSGNJ-NEXT: ret
3212+
%z = call half @llvm.copysign.f16(half 1.0, half %x)
3213+
%mul = fmul half %z, %y
3214+
ret half %mul
3215+
}

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