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If the ESP32 interrupt service routine (ISR) is placed in IRAM (using ESP_INTR_FLAG_IRAM), the CPU cannot access Flash during the execution of the ISR (because IRAM code must be executed without delay).
NVS operations (such as nvs_get_* and nvs_set_*) require Flash access. If an IRAM ISR is running, NVS operations may fail or cause a deadlock.
NVS Depends on Flash Operations:
NVS relies on SPI Flash at the lower level. Flash access may be blocked during IRAM ISR execution, leading to NVS read/write failures.
Interrupt Priority Issues:
If the MCPWM interrupt has a higher priority and is triggered frequently, it may prevent NVS operations from completing in a timely manner.
The text was updated successfully, but these errors were encountered:
SimpleFOC needs the interrupts for current sensing. They are placed in IRAM to ensure they execute quickly, which is also important.
As a workaround I would suggest handling nvm access before initialising the current sense, if possible.
Since S3 MCU has two cores you could also investigate if it is possible to handle the SimpleFOC interrupts on one core, and the nvmram ones on the other.
Otherwise, if you have suggestions for an improvement that keeps the ADC performance but avoids this problem, I'd be interested to learn.
nvs not good work,when i use simplefoc,this is a issue:
void _driverSyncLowSide(void* driver_params, void* cs_params){
mcpwm_dev_t* mcpwm_dev = ((ESP32MCPWMDriverParams*)driver_params)->mcpwm_dev;
mcpwm_unit_t mcpwm_unit = ((ESP32MCPWMDriverParams*)driver_params)->mcpwm_unit;
mcpwm_dev->int_ena.timer0_tep_int_ena = true;//A PWM timer 0 TEP event will trigger this interrupt
// mcpwm_dev->int_ena.timer0_tep_int_ena = true;//A PWM timer 0 TEZ event will trigger this interrupt
if(mcpwm_unit == MCPWM_UNIT_0)
{
mcpwm_isr_register(mcpwm_unit, mcpwm0_isr_handler, NULL, ESP_INTR_FLAG_IRAM, NULL); //Set ISR Handler
}
else
mcpwm_isr_register(mcpwm_unit, mcpwm1_isr_handler, NULL, ESP_INTR_FLAG_IRAM, NULL); //Set ISR Handler
}
Why does
ESP_INTR_FLAG_IRAM
affect NVS?IRAM Interrupts Disable Flash Access:
If the ESP32 interrupt service routine (ISR) is placed in IRAM (using
ESP_INTR_FLAG_IRAM
), the CPU cannot access Flash during the execution of the ISR (because IRAM code must be executed without delay).NVS operations (such as
nvs_get_*
andnvs_set_*
) require Flash access. If an IRAM ISR is running, NVS operations may fail or cause a deadlock.NVS Depends on Flash Operations:
NVS relies on SPI Flash at the lower level. Flash access may be blocked during IRAM ISR execution, leading to NVS read/write failures.
Interrupt Priority Issues:
If the MCPWM interrupt has a higher priority and is triggered frequently, it may prevent NVS operations from completing in a timely manner.
The text was updated successfully, but these errors were encountered: