|
| 1 | +# Feature Name |
| 2 | +PCS Error Counters |
| 3 | +# High Level Design Document |
| 4 | +#### Rev 0.1 |
| 5 | + |
| 6 | +# Table of Contents |
| 7 | + * [List of Tables](#list-of-tables) |
| 8 | + * [Revision](#revision) |
| 9 | + * [About This Manual](#about-this-manual) |
| 10 | + * [Scope](#scope) |
| 11 | + * [Definition/Abbreviation](#definitionabbreviation) |
| 12 | + |
| 13 | +# List of Tables |
| 14 | +[Table 1: Abbreviations](#table-1-abbreviations) |
| 15 | + |
| 16 | +# Revision |
| 17 | +| Rev | Date | Author | Change Description | |
| 18 | +|:---:|:-----------:|:------------------:|-----------------------------------| |
| 19 | +| 0.1 | 04/14/2021 | Steven Lu | Initial version for requirements | |
| 20 | + |
| 21 | +# About this Manual |
| 22 | +This document provides general information about the PCS Error counters feature implementation in SONiC. |
| 23 | +# Scope |
| 24 | +This document describes the high level design of PCS Error counters feature. Call out any related design that is not covered by this document |
| 25 | + |
| 26 | +# Definition/Abbreviation |
| 27 | + |
| 28 | +### Table 1: Abbreviations |
| 29 | +| **Term** | **Meaning** | |
| 30 | +|--------------------------|-------------------------------------| |
| 31 | +| XYZ | Term description | |
| 32 | + |
| 33 | +# 1 Feature Overview |
| 34 | +The PCS Error counters feature collects PCS Errors from Brcm silicons and help customers determine condition of physcial ethernet link |
| 35 | + |
| 36 | + |
| 37 | + |
| 38 | +## 1.1 Requirements |
| 39 | +PCS Error counters feature should cover Broadcom silicons include Tomahawk-1, Tomahawk-2, Trident-3 and Tomahawk-3 |
| 40 | +SONiC shall be able collect PCS Error counters of individual port |
| 41 | +SONiC shall be able to display PCS Error counters of individual port |
| 42 | +PCS error counters should be collected at same rate as other counters. |
| 43 | +Below PCS counters should be collected: |
| 44 | +- For 10G/40G/100G NRZ without FEC |
| 45 | + Errored Block Count |
| 46 | + BER Count |
| 47 | +- For PAM4 ports or ports with RS FEC enabled |
| 48 | + FEC correctable errors |
| 49 | + FEC uncorrectable errors |
| 50 | + |
| 51 | +### 1.1.1 Functional Requirements |
| 52 | + |
| 53 | + |
| 54 | +### 1.1.3 Scalability Requirements |
| 55 | +PCS Error counters feature shall be supported on all physcial ports. All the platform design, SDK, and ASIC constraints should be considered. |
| 56 | + |
| 57 | + |
| 58 | +### 1.1.4 Warm Boot Requirements |
| 59 | +Interfaces PCS Error counters must be retained across warmboot. |
| 60 | + |
| 61 | + |
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