Misaligned load and store instruction

[kasanovic]

Zicclsm Misaligned loads and stores are supported (i.e., no visible trap) to main memory regions with cacheability and coherence

[allenjbaum]

Just to be clear: this is regardless of cache line or page boundary crossing? (obviously crossing protectin boundaries may trap if the access crosses into a protected region - which is a spearate option: do sotres perform the first part before trapping?

[kasanovic]

Yes, regardless of any crossings.
The existing ISA spec describes the possible behaviors of an execution environment around misaligned traps.